\subsubsection{ConfigReg}
\index{ConfigReg@\te{ConfigReg} (package,interface)}
\index{mkConfigReg@\te{mkConfigReg} (module)}
\index{mkConfigRegA@\te{mkConfigRegA} (module)}
\index{mkConfigRegU@\te{mkConfigRegU} (module)}
\label{ref-configreg}

{\bf Package}

\begin{verbatim}
import ConfigReg :: * ;
\end{verbatim}



{\bf Description}


The \te{ConfigReg} package provides a way to create registers where
each  update clobbers the current value, but the precise timing of
updates  is not important.  These registers are identical to the
\te{mkReg} registers except that their scheduling annotations allows
reads and writes to occur in either order during rule execution.  

Rules which fire during the clock cycle where the register is written
read a stale value (that is the value from the beginning of the clock
cycle) regardless of firing order and writes which have occurred
during the clock cycle.  Thus
if rule \te{r1} writes to a ConfigReg \te{cr} and rule \te{r2} reads
\te{cr} later in the same cycle, the old or stale value of \te{cr} is
read, not the value written in \te{r1}.  If a standard register is
used instead, rule \te{r2}'s execution will be blocked by \te{r1}'s
execution or the scheduler may create a different rule execution order.

The hardware implementation is identical for the more common
registers (\te{mkReg}, \te{mkRegU} and \te{mkRegA}), and the module constructors
parallel these as well.

{\bf Interfaces}

 The \te{ConfigReg} interface is an alias of the \te{Reg} interface
%  (sections \ref{sec-registers} and
(section \ref{lib-registers}).
\begin{libverbatim}
typedef Reg#(a_type) ConfigReg #(type a_type);
\end{libverbatim}


{\bf Modules}

The \te{ConfigReg} package provides three modules; \te{mkConfigReg}
creates a register with a given reset value and synchronous reset
logic, \te{mkConfigRegU} creates a register without any reset, and
\te{mkConfigRegA} creates a register with a given reset value and
asynchronous reset logic.

\begin{tabular}{|p{1.2 in}|p{4.4 in}|}
\hline
&\\
\te{mkConfigReg}&Make a register with a given reset value.  Reset logic is synchronous\\
\cline{2-2}
&\begin{libverbatim}
module mkConfigReg#(a_type resetval)(Reg#(a_type))
  provisos (Bits#(a_type, sizea));
\end{libverbatim}
\\
\hline
\end{tabular}




\begin{tabular}{|p{1.2 in}|p{4.4 in}|}
\hline
&\\
\te{mkConfigRegU}&Make a register without any reset; initial simulation value is alternating 01 bits.\\
\cline{2-2}
&\begin{libverbatim}
module mkConfigRegU(Reg#(a_type))
  provisos (Bits#(a_type, sizea));
\end{libverbatim}
\\
\hline
\end{tabular}

\begin{tabular}{|p{1.2 in}|p{4.4 in}|}
\hline
&\\
\te{mkConfigRegA}&Make a register with a given reset value.  Reset logic is asynchronous.\\
\cline{2-2}
&\begin{libverbatim}
module mkConfigRegA#(a_type, resetval)(Reg#(a_type))
  provisos (Bits#(a_type, sizea));
\end{libverbatim}
\\
\hline
\end{tabular}

\begin{center}
\begin{tabular}{|p{.75 in}|c|c|}
\hline
\multicolumn{3}{|c|}{Scheduling Annotations}\\
\multicolumn{3}{|c|}{mkConfigReg, mkConfigRegU, mkConfigRegA}\\
\hline
&{read}&{write}\\
\hline
\hline
{read}&CF&CF\\
\hline
{write}&CF& SBR\\
\hline
\hline
\end{tabular}
\end{center}