# -------------------------

INSTALL_NAME = Verilog.Vivado

VERI_FILES = \
	MakeClock.v \
	RegFile.v \
	SizedFIFO.v \
	BRAM1.v \
	BRAM1BE.v \
	BRAM1BELoad.v \
	BRAM1Load.v \
	BRAM2.v \
	BRAM2BE.v \
	BRAM2BELoad.v \
	BRAM2Load.v \

OTHER_FILES = \

VCD_TEST_MODS = \

include ../Verilog/common.mk

# -------------------------