//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 reset
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module sysDisplayDynConstArray(CLK,
			       RST_N);
  input  CLK;
  input  RST_N;

  // register c
  reg c;
  wire c$D_IN, c$EN;

  // register idx
  reg [1 : 0] idx;
  wire [1 : 0] idx$D_IN;
  wire idx$EN;

  // remaining internal signals
  reg [7 : 0] CASE_idx_0_IF_c_THEN_1_ELSE_4_1_IF_c_THEN_2_EL_ETC__q1;

  // register c
  assign c$D_IN = 1'b0 ;
  assign c$EN = 1'b0 ;

  // register idx
  assign idx$D_IN = 2'h0 ;
  assign idx$EN = 1'b0 ;

  // remaining internal signals
  always@(idx or c)
  begin
    case (idx)
      2'd0:
	  CASE_idx_0_IF_c_THEN_1_ELSE_4_1_IF_c_THEN_2_EL_ETC__q1 =
	      c ? 8'd1 : 8'd4;
      2'd1:
	  CASE_idx_0_IF_c_THEN_1_ELSE_4_1_IF_c_THEN_2_EL_ETC__q1 =
	      c ? 8'd2 : 8'd3;
      2'd2:
	  CASE_idx_0_IF_c_THEN_1_ELSE_4_1_IF_c_THEN_2_EL_ETC__q1 =
	      c ? 8'd3 : 8'd2;
      2'd3:
	  CASE_idx_0_IF_c_THEN_1_ELSE_4_1_IF_c_THEN_2_EL_ETC__q1 =
	      c ? 8'd4 : 8'd1;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        c <= `BSV_ASSIGNMENT_DELAY 1'd1;
	idx <= `BSV_ASSIGNMENT_DELAY 2'd0;
      end
    else
      begin
        if (c$EN) c <= `BSV_ASSIGNMENT_DELAY c$D_IN;
	if (idx$EN) idx <= `BSV_ASSIGNMENT_DELAY idx$D_IN;
      end
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    c = 1'h0;
    idx = 2'h2;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      $display(CASE_idx_0_IF_c_THEN_1_ELSE_4_1_IF_c_THEN_2_EL_ETC__q1);
  end
  // synopsys translate_on
endmodule  // sysDisplayDynConstArray