//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// RDY_write                      O     1 const
// read                           O     8
// RDY_read                       O     1 const
// CLK                            I     1 clock
// RST_N                          I     1 reset
// write_idx                      I     3
// write_val                      I     8
// read_idx                       I     3
// EN_write                       I     1
//
// Combinational paths from inputs to outputs:
//   read_idx -> read
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module sysRegOfVec(CLK,
		   RST_N,

		   write_idx,
		   write_val,
		   EN_write,
		   RDY_write,

		   read_idx,
		   read,
		   RDY_read);
  input  CLK;
  input  RST_N;

  // action method write
  input  [2 : 0] write_idx;
  input  [7 : 0] write_val;
  input  EN_write;
  output RDY_write;

  // value method read
  input  [2 : 0] read_idx;
  output [7 : 0] read;
  output RDY_read;

  // signals for module outputs
  reg [7 : 0] read;
  wire RDY_read, RDY_write;

  // register rg
  reg [63 : 0] rg;
  wire [63 : 0] rg$D_IN;
  wire rg$EN;

  // remaining internal signals
  wire [47 : 0] IF_write_idx_EQ_7_THEN_write_val_ELSE_rg_BITS__ETC___d22;
  wire [31 : 0] IF_write_idx_EQ_7_THEN_write_val_ELSE_rg_BITS__ETC___d15;

  // action method write
  assign RDY_write = 1'd1 ;

  // value method read
  always@(read_idx or rg)
  begin
    case (read_idx)
      3'd0: read = rg[7:0];
      3'd1: read = rg[15:8];
      3'd2: read = rg[23:16];
      3'd3: read = rg[31:24];
      3'd4: read = rg[39:32];
      3'd5: read = rg[47:40];
      3'd6: read = rg[55:48];
      3'd7: read = rg[63:56];
    endcase
  end
  assign RDY_read = 1'd1 ;

  // register rg
  assign rg$D_IN =
	     { IF_write_idx_EQ_7_THEN_write_val_ELSE_rg_BITS__ETC___d22,
	       (write_idx == 3'd1) ? write_val : rg[15:8],
	       (write_idx == 3'd0) ? write_val : rg[7:0] } ;
  assign rg$EN = EN_write ;

  // remaining internal signals
  assign IF_write_idx_EQ_7_THEN_write_val_ELSE_rg_BITS__ETC___d15 =
	     { (write_idx == 3'd7) ? write_val : rg[63:56],
	       (write_idx == 3'd6) ? write_val : rg[55:48],
	       (write_idx == 3'd5) ? write_val : rg[47:40],
	       (write_idx == 3'd4) ? write_val : rg[39:32] } ;
  assign IF_write_idx_EQ_7_THEN_write_val_ELSE_rg_BITS__ETC___d22 =
	     { IF_write_idx_EQ_7_THEN_write_val_ELSE_rg_BITS__ETC___d15,
	       (write_idx == 3'd3) ? write_val : rg[31:24],
	       (write_idx == 3'd2) ? write_val : rg[23:16] } ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        rg <= `BSV_ASSIGNMENT_DELAY 64'd0;
      end
    else
      begin
        if (rg$EN) rg <= `BSV_ASSIGNMENT_DELAY rg$D_IN;
      end
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    rg = 64'hAAAAAAAAAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // sysRegOfVec