//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 reset
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module sysRegToReg(CLK,
		   RST_N);
  input  CLK;
  input  RST_N;

  // register done
  reg done;
  wire done$D_IN, done$EN;

  // register idx
  reg [2 : 0] idx;
  wire [2 : 0] idx$D_IN;
  wire idx$EN;

  // register rg
  reg [63 : 0] rg;
  wire [63 : 0] rg$D_IN;
  wire rg$EN;

  // remaining internal signals
  wire [47 : 0] IF_idx_EQ_7_THEN_0_CONCAT_idx_PLUS_1_ELSE_rg_B_ETC___d27;
  wire [31 : 0] IF_idx_EQ_7_THEN_0_CONCAT_idx_PLUS_1_ELSE_rg_B_ETC___d20;
  wire [7 : 0] _0_CONCAT_idx_PLUS_1___d35;

  // register done
  assign done$D_IN = 1'd1 ;
  assign done$EN = !done && idx == 3'd7 ;

  // register idx
  assign idx$D_IN = 3'h0 ;
  assign idx$EN = 1'b0 ;

  // register rg
  assign rg$D_IN =
	     { IF_idx_EQ_7_THEN_0_CONCAT_idx_PLUS_1_ELSE_rg_B_ETC___d27,
	       (idx == 3'd1) ? _0_CONCAT_idx_PLUS_1___d35 : rg[15:8],
	       (idx == 3'd0) ? _0_CONCAT_idx_PLUS_1___d35 : rg[7:0] } ;
  assign rg$EN = !done ;

  // remaining internal signals
  assign IF_idx_EQ_7_THEN_0_CONCAT_idx_PLUS_1_ELSE_rg_B_ETC___d20 =
	     { (idx == 3'd7) ? _0_CONCAT_idx_PLUS_1___d35 : rg[63:56],
	       (idx == 3'd6) ? _0_CONCAT_idx_PLUS_1___d35 : rg[55:48],
	       (idx == 3'd5) ? _0_CONCAT_idx_PLUS_1___d35 : rg[47:40],
	       (idx == 3'd4) ? _0_CONCAT_idx_PLUS_1___d35 : rg[39:32] } ;
  assign IF_idx_EQ_7_THEN_0_CONCAT_idx_PLUS_1_ELSE_rg_B_ETC___d27 =
	     { IF_idx_EQ_7_THEN_0_CONCAT_idx_PLUS_1_ELSE_rg_B_ETC___d20,
	       (idx == 3'd3) ? _0_CONCAT_idx_PLUS_1___d35 : rg[31:24],
	       (idx == 3'd2) ? _0_CONCAT_idx_PLUS_1___d35 : rg[23:16] } ;
  assign _0_CONCAT_idx_PLUS_1___d35 = { 5'd0, idx } + 8'd1 ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        done <= `BSV_ASSIGNMENT_DELAY 1'd0;
	idx <= `BSV_ASSIGNMENT_DELAY 3'd0;
	rg <= `BSV_ASSIGNMENT_DELAY 64'd0;
      end
    else
      begin
        if (done$EN) done <= `BSV_ASSIGNMENT_DELAY done$D_IN;
	if (idx$EN) idx <= `BSV_ASSIGNMENT_DELAY idx$D_IN;
	if (rg$EN) rg <= `BSV_ASSIGNMENT_DELAY rg$D_IN;
      end
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    done = 1'h0;
    idx = 3'h2;
    rg = 64'hAAAAAAAAAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE) if (done) $finish(32'd0);
  end
  // synopsys translate_on
endmodule  // sysRegToReg