//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 reset
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module sysVecCondAction(CLK,
			RST_N);
  input  CLK;
  input  RST_N;

  // register idx
  reg [1 : 0] idx;
  wire [1 : 0] idx$D_IN;
  wire idx$EN;

  // register rgs_0
  reg rgs_0;
  wire rgs_0$D_IN, rgs_0$EN;

  // register rgs_1
  reg rgs_1;
  wire rgs_1$D_IN, rgs_1$EN;

  // register rgs_2
  reg rgs_2;
  wire rgs_2$D_IN, rgs_2$EN;

  // ports of submodule f
  wire [7 : 0] f$D_IN;
  wire f$CLR, f$DEQ, f$ENQ, f$FULL_N;

  // remaining internal signals
  reg CASE_idx_0_rgs_0_1_rgs_1_2_rgs_2_3_DONTCARE_DO_ETC__q1;

  // submodule f
  FIFO2 #(.width(32'd8), .guarded(1'd1)) f(.RST(RST_N),
					   .CLK(CLK),
					   .D_IN(f$D_IN),
					   .ENQ(f$ENQ),
					   .DEQ(f$DEQ),
					   .CLR(f$CLR),
					   .D_OUT(),
					   .FULL_N(f$FULL_N),
					   .EMPTY_N());

  // register idx
  assign idx$D_IN = 2'h0 ;
  assign idx$EN = 1'b0 ;

  // register rgs_0
  assign rgs_0$D_IN = 1'b0 ;
  assign rgs_0$EN = 1'b0 ;

  // register rgs_1
  assign rgs_1$D_IN = 1'b0 ;
  assign rgs_1$EN = 1'b0 ;

  // register rgs_2
  assign rgs_2$D_IN = 1'b0 ;
  assign rgs_2$EN = 1'b0 ;

  // submodule f
  assign f$D_IN = 8'd0 ;
  assign f$ENQ =
	     f$FULL_N &&
	     CASE_idx_0_rgs_0_1_rgs_1_2_rgs_2_3_DONTCARE_DO_ETC__q1 ;
  assign f$DEQ = 1'b0 ;
  assign f$CLR = 1'b0 ;

  // remaining internal signals
  always@(idx or rgs_0 or rgs_1 or rgs_2)
  begin
    case (idx)
      2'd0: CASE_idx_0_rgs_0_1_rgs_1_2_rgs_2_3_DONTCARE_DO_ETC__q1 = rgs_0;
      2'd1: CASE_idx_0_rgs_0_1_rgs_1_2_rgs_2_3_DONTCARE_DO_ETC__q1 = rgs_1;
      2'd2: CASE_idx_0_rgs_0_1_rgs_1_2_rgs_2_3_DONTCARE_DO_ETC__q1 = rgs_2;
      2'd3:
	  CASE_idx_0_rgs_0_1_rgs_1_2_rgs_2_3_DONTCARE_DO_ETC__q1 =
	      1'b0 /* unspecified value */ ;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        idx <= `BSV_ASSIGNMENT_DELAY 2'd0;
      end
    else
      begin
        if (idx$EN) idx <= `BSV_ASSIGNMENT_DELAY idx$D_IN;
      end
    if (rgs_0$EN) rgs_0 <= `BSV_ASSIGNMENT_DELAY rgs_0$D_IN;
    if (rgs_1$EN) rgs_1 <= `BSV_ASSIGNMENT_DELAY rgs_1$D_IN;
    if (rgs_2$EN) rgs_2 <= `BSV_ASSIGNMENT_DELAY rgs_2$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    idx = 2'h2;
    rgs_0 = 1'h0;
    rgs_1 = 1'h0;
    rgs_2 = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // sysVecCondAction