-verilog
mkIfcWithVec mkI mkM mkT
----------
Command: module porttypes mkT
i Inout#(Test::Bar)
CLK Clock
RST_N Reset
r__write_1 Bool
EN_r__write Bool
RDY_r__write Bool
r__read Bool
RDY_r__read Bool
b Inout#(Test::Bar)
---------

Command: module porttypes mkM
CLK Clock
RST_N Reset
_write_1 Bool
EN__write Bool
RDY__write Bool
_read Bool
RDY__read Bool
---------

Command: module porttypes mkIfcWithVec
io Inout#(Test::Bar)
CLK Clock
RST_N Reset
vec1_0__write_1 Bool
EN_vec1_0__write Bool
RDY_vec1_0__write Bool
vec1_0__read Bool
RDY_vec1_0__read Bool
vec1_1__write_1 Bool
EN_vec1_1__write Bool
RDY_vec1_1__write Bool
vec1_1__read Bool
RDY_vec1_1__read Bool
vec2_0_0__write_1 Bool
EN_vec2_0_0__write Bool
RDY_vec2_0_0__write Bool
vec2_0_0__read Bool
RDY_vec2_0_0__read Bool
vec2_0_1__write_1 Bool
EN_vec2_0_1__write Bool
RDY_vec2_0_1__write Bool
vec2_0_1__read Bool
RDY_vec2_0_1__read Bool
vec2_1_0__write_1 Bool
EN_vec2_1_0__write Bool
RDY_vec2_1_0__write Bool
vec2_1_0__read Bool
RDY_vec2_1_0__read Bool
vec2_1_1__write_1 Bool
EN_vec2_1_1__write Bool
RDY_vec2_1_1__write Bool
vec2_1_1__read Bool
RDY_vec2_1_1__read Bool
vec3_0_0_0__write_1 Bool
EN_vec3_0_0_0__write Bool
RDY_vec3_0_0_0__write Bool
vec3_0_0_0__read Bool
RDY_vec3_0_0_0__read Bool
vec3_0_0_1__write_1 Bool
EN_vec3_0_0_1__write Bool
RDY_vec3_0_0_1__write Bool
vec3_0_0_1__read Bool
RDY_vec3_0_0_1__read Bool
vec3_0_1_0__write_1 Bool
EN_vec3_0_1_0__write Bool
RDY_vec3_0_1_0__write Bool
vec3_0_1_0__read Bool
RDY_vec3_0_1_0__read Bool
vec3_0_1_1__write_1 Bool
EN_vec3_0_1_1__write Bool
RDY_vec3_0_1_1__write Bool
vec3_0_1_1__read Bool
RDY_vec3_0_1_1__read Bool
vec3_1_0_0__write_1 Bool
EN_vec3_1_0_0__write Bool
RDY_vec3_1_0_0__write Bool
vec3_1_0_0__read Bool
RDY_vec3_1_0_0__read Bool
vec3_1_0_1__write_1 Bool
EN_vec3_1_0_1__write Bool
RDY_vec3_1_0_1__write Bool
vec3_1_0_1__read Bool
RDY_vec3_1_0_1__read Bool
vec3_1_1_0__write_1 Bool
EN_vec3_1_1_0__write Bool
RDY_vec3_1_1_0__write Bool
vec3_1_1_0__read Bool
RDY_vec3_1_1_0__read Bool
vec3_1_1_1__write_1 Bool
EN_vec3_1_1_1__write Bool
RDY_vec3_1_1_1__write Bool
vec3_1_1_1__read Bool
RDY_vec3_1_1_1__read Bool
data1 {Vector::Vector#(2, Bool)}
RDY_data1 Bool
data2 {Vector::Vector#(2, Vector::Vector#(2, Bool))}
RDY_data2 Bool
data3 {Vector::Vector#(2, Vector::Vector#(2, Vector::Vector#(2, Bool)))}
RDY_data3 Bool
CLK_clks1_0 Clock
CLK_GATE_clks1_0 Bool
CLK_clks1_1 Clock
CLK_GATE_clks1_1 Bool
RST_N_rsts1_0 Reset
RST_N_rsts1_1 Reset
ios1_0 Inout#(Test::Bar)
ios1_1 Inout#(Test::Bar)
---------
----------
module ports mkT
Command: module ports mkT
interface {{interface r {{method _write r__write {clock default_clock} {reset no_reset} {args {{{name r__write_1} {port r__write_1} {size 1}}}} {enable EN_r__write} {ready RDY_r__write}} {method _read r__read {clock no_clock} {reset no_reset} {args {}} {result r__read} {ready RDY_r__read}}}} {inout b b {port b} {clock default_clock} {reset default_reset}}}
args {{inout i {port i} {clock default_clock} {reset default_reset} {size 2}} {clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}
---------

module ports mkM
Command: module ports mkM
interface {{method _write _write {clock default_clock} {reset default_reset} {args {{{name _write_1} {port _write_1} {size 1}}}} {enable EN__write} {ready RDY__write}} {method _read _read {clock default_clock} {reset default_reset} {args {}} {result _read} {ready RDY__read}}}
args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}
---------

module ports mkIfcWithVec
Command: module ports mkIfcWithVec
interface {{interface vec1 {{interface 0 {{method _write vec1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec1_0__write_1} {port vec1_0__write_1} {size 1}}}} {enable EN_vec1_0__write} {ready RDY_vec1_0__write}} {method _read vec1_0__read {clock no_clock} {reset no_reset} {args {}} {result vec1_0__read} {ready RDY_vec1_0__read}}}} {interface 1 {{method _write vec1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec1_1__write_1} {port vec1_1__write_1} {size 1}}}} {enable EN_vec1_1__write} {ready RDY_vec1_1__write}} {method _read vec1_1__read {clock no_clock} {reset no_reset} {args {}} {result vec1_1__read} {ready RDY_vec1_1__read}}}}}} {interface vec2 {{interface 0 {{interface 0 {{method _write vec2_0_0__write {clock clks1_1} {reset no_reset} {args {{{name vec2_0_0__write_1} {port vec2_0_0__write_1} {size 1}}}} {enable EN_vec2_0_0__write} {ready RDY_vec2_0_0__write}} {method _read vec2_0_0__read {clock no_clock} {reset no_reset} {args {}} {result vec2_0_0__read} {ready RDY_vec2_0_0__read}}}} {interface 1 {{method _write vec2_0_1__write {clock clks1_1} {reset no_reset} {args {{{name vec2_0_1__write_1} {port vec2_0_1__write_1} {size 1}}}} {enable EN_vec2_0_1__write} {ready RDY_vec2_0_1__write}} {method _read vec2_0_1__read {clock no_clock} {reset no_reset} {args {}} {result vec2_0_1__read} {ready RDY_vec2_0_1__read}}}}}} {interface 1 {{interface 0 {{method _write vec2_1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec2_1_0__write_1} {port vec2_1_0__write_1} {size 1}}}} {enable EN_vec2_1_0__write} {ready RDY_vec2_1_0__write}} {method _read vec2_1_0__read {clock no_clock} {reset no_reset} {args {}} {result vec2_1_0__read} {ready RDY_vec2_1_0__read}}}} {interface 1 {{method _write vec2_1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec2_1_1__write_1} {port vec2_1_1__write_1} {size 1}}}} {enable EN_vec2_1_1__write} {ready RDY_vec2_1_1__write}} {method _read vec2_1_1__read {clock no_clock} {reset no_reset} {args {}} {result vec2_1_1__read} {ready RDY_vec2_1_1__read}}}}}}}} {interface vec3 {{interface 0 {{interface 0 {{interface 0 {{method _write vec3_0_0_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_0_0__write_1} {port vec3_0_0_0__write_1} {size 1}}}} {enable EN_vec3_0_0_0__write} {ready RDY_vec3_0_0_0__write}} {method _read vec3_0_0_0__read {clock no_clock} {reset no_reset} {args {}} {result vec3_0_0_0__read} {ready RDY_vec3_0_0_0__read}}}} {interface 1 {{method _write vec3_0_0_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_0_1__write_1} {port vec3_0_0_1__write_1} {size 1}}}} {enable EN_vec3_0_0_1__write} {ready RDY_vec3_0_0_1__write}} {method _read vec3_0_0_1__read {clock no_clock} {reset no_reset} {args {}} {result vec3_0_0_1__read} {ready RDY_vec3_0_0_1__read}}}}}} {interface 1 {{interface 0 {{method _write vec3_0_1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_1_0__write_1} {port vec3_0_1_0__write_1} {size 1}}}} {enable EN_vec3_0_1_0__write} {ready RDY_vec3_0_1_0__write}} {method _read vec3_0_1_0__read {clock no_clock} {reset no_reset} {args {}} {result vec3_0_1_0__read} {ready RDY_vec3_0_1_0__read}}}} {interface 1 {{method _write vec3_0_1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_1_1__write_1} {port vec3_0_1_1__write_1} {size 1}}}} {enable EN_vec3_0_1_1__write} {ready RDY_vec3_0_1_1__write}} {method _read vec3_0_1_1__read {clock no_clock} {reset no_reset} {args {}} {result vec3_0_1_1__read} {ready RDY_vec3_0_1_1__read}}}}}}}} {interface 1 {{interface 0 {{interface 0 {{method _write vec3_1_0_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_0_0__write_1} {port vec3_1_0_0__write_1} {size 1}}}} {enable EN_vec3_1_0_0__write} {ready RDY_vec3_1_0_0__write}} {method _read vec3_1_0_0__read {clock no_clock} {reset no_reset} {args {}} {result vec3_1_0_0__read} {ready RDY_vec3_1_0_0__read}}}} {interface 1 {{method _write vec3_1_0_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_0_1__write_1} {port vec3_1_0_1__write_1} {size 1}}}} {enable EN_vec3_1_0_1__write} {ready RDY_vec3_1_0_1__write}} {method _read vec3_1_0_1__read {clock no_clock} {reset no_reset} {args {}} {result vec3_1_0_1__read} {ready RDY_vec3_1_0_1__read}}}}}} {interface 1 {{interface 0 {{method _write vec3_1_1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_1_0__write_1} {port vec3_1_1_0__write_1} {size 1}}}} {enable EN_vec3_1_1_0__write} {ready RDY_vec3_1_1_0__write}} {method _read vec3_1_1_0__read {clock no_clock} {reset no_reset} {args {}} {result vec3_1_1_0__read} {ready RDY_vec3_1_1_0__read}}}} {interface 1 {{method _write vec3_1_1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_1_1__write_1} {port vec3_1_1_1__write_1} {size 1}}}} {enable EN_vec3_1_1_1__write} {ready RDY_vec3_1_1_1__write}} {method _read vec3_1_1_1__read {clock no_clock} {reset no_reset} {args {}} {result vec3_1_1_1__read} {ready RDY_vec3_1_1_1__read}}}}}}}}}} {method data1 data1 {clock no_clock} {reset no_reset} {args {}} {result data1} {ready RDY_data1}} {method data2 data2 {clock no_clock} {reset no_reset} {args {}} {result data2} {ready RDY_data2}} {method data3 data3 {clock no_clock} {reset no_reset} {args {}} {result data3} {ready RDY_data3}} {interface clks1 {{interface 0 {{clock {} clks1_0 {osc CLK_clks1_0} {gate CLK_GATE_clks1_0}}}} {interface 1 {{clock {} clks1_1 {osc CLK_clks1_1} {gate CLK_GATE_clks1_1}}}}}} {interface rsts1 {{interface 0 {{reset {} rsts1_0 {port RST_N_rsts1_0} {clock default_clock}}}} {interface 1 {{reset {} rsts1_1 {port RST_N_rsts1_1} {clock default_clock}}}}}} {interface ios1 {{interface 0 {{inout {} ios1_0 {port ios1_0} {clock clks1_1} {reset rsts1_1}}}} {interface 1 {{inout {} ios1_1 {port ios1_1} {clock clks1_1} {reset rsts1_1}}}}}}}
args {{inout io {port io} {clock default_clock} {reset default_reset} {size 2}} {clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}
---------
----------