-verilog mkIfcWithVec mkI mkM mkT ---------- Command: submodule ports mkT r1 mkM interface method _write _write clock default_clock reset default_reset args {{{port _write_1} {size 1}}} enable EN__write ready RDY__write method _read _read clock default_clock reset default_reset args {} result _read ready RDY__read args clock default_clock {osc CLK} reset default_reset port RST_N clock default_clock r2 mkM interface method _write _write clock default_clock reset default_reset args {{{port _write_1} {size 1}}} enable EN__write ready RDY__write method _read _read clock default_clock reset default_reset args {} result _read ready RDY__read args clock default_clock {osc CLK} reset default_reset port RST_N clock default_clock mi mkI interface {inout b b {port b} {clock default_clock} {reset default_reset}} args inout i port i clock default_clock reset default_reset size 2 clock default_clock {osc CLK} reset default_reset port RST_N clock default_clock mb VFoo interface method wset wset clock clk reset rst args {{{port WVAL} {size 4}}} enable WSET method wget wget clock clk reset rst args {} result WGET method whas whas clock clk reset rst args {} result WHAS inout io_out io_out port I_OUT clock clk reset rst args parameter width {param width} clock clk reset rst {clock clk} port V {port V} {clock clk} {reset rst} {size 32} inout I_IN port I_IN clock clk reset rst size 2 iv mkIfcWithVec interface interface vec1 interface 0 method _write vec1_0__write clock clks1_1 reset no_reset args {{{port vec1_0__write_1} {size 1}}} enable EN_vec1_0__write ready RDY_vec1_0__write method _read vec1_0__read clock no_clock reset no_reset args {} result vec1_0__read ready RDY_vec1_0__read interface 1 method _write vec1_1__write clock clks1_1 reset no_reset args {{{port vec1_1__write_1} {size 1}}} enable EN_vec1_1__write ready RDY_vec1_1__write method _read vec1_1__read clock no_clock reset no_reset args {} result vec1_1__read ready RDY_vec1_1__read interface vec2 interface 0 interface 0 method _write vec2_0_0__write clock clks1_1 reset no_reset args {{{port vec2_0_0__write_1} {size 1}}} enable EN_vec2_0_0__write ready RDY_vec2_0_0__write method _read vec2_0_0__read clock no_clock reset no_reset args {} result vec2_0_0__read ready RDY_vec2_0_0__read interface 1 method _write vec2_0_1__write clock clks1_1 reset no_reset args {{{port vec2_0_1__write_1} {size 1}}} enable EN_vec2_0_1__write ready RDY_vec2_0_1__write method _read vec2_0_1__read clock no_clock reset no_reset args {} result vec2_0_1__read ready RDY_vec2_0_1__read interface 1 interface 0 method _write vec2_1_0__write clock clks1_1 reset no_reset args {{{port vec2_1_0__write_1} {size 1}}} enable EN_vec2_1_0__write ready RDY_vec2_1_0__write method _read vec2_1_0__read clock no_clock reset no_reset args {} result vec2_1_0__read ready RDY_vec2_1_0__read interface 1 method _write vec2_1_1__write clock clks1_1 reset no_reset args {{{port vec2_1_1__write_1} {size 1}}} enable EN_vec2_1_1__write ready RDY_vec2_1_1__write method _read vec2_1_1__read clock no_clock reset no_reset args {} result vec2_1_1__read ready RDY_vec2_1_1__read interface vec3 interface 0 interface 0 interface 0 method _write vec3_0_0_0__write clock clks1_1 reset no_reset args {{{port vec3_0_0_0__write_1} {size 1}}} enable EN_vec3_0_0_0__write ready RDY_vec3_0_0_0__write method _read vec3_0_0_0__read clock no_clock reset no_reset args {} result vec3_0_0_0__read ready RDY_vec3_0_0_0__read interface 1 method _write vec3_0_0_1__write clock clks1_1 reset no_reset args {{{port vec3_0_0_1__write_1} {size 1}}} enable EN_vec3_0_0_1__write ready RDY_vec3_0_0_1__write method _read vec3_0_0_1__read clock no_clock reset no_reset args {} result vec3_0_0_1__read ready RDY_vec3_0_0_1__read interface 1 interface 0 method _write vec3_0_1_0__write clock clks1_1 reset no_reset args {{{port vec3_0_1_0__write_1} {size 1}}} enable EN_vec3_0_1_0__write ready RDY_vec3_0_1_0__write method _read vec3_0_1_0__read clock no_clock reset no_reset args {} result vec3_0_1_0__read ready RDY_vec3_0_1_0__read interface 1 method _write vec3_0_1_1__write clock clks1_1 reset no_reset args {{{port vec3_0_1_1__write_1} {size 1}}} enable EN_vec3_0_1_1__write ready RDY_vec3_0_1_1__write method _read vec3_0_1_1__read clock no_clock reset no_reset args {} result vec3_0_1_1__read ready RDY_vec3_0_1_1__read interface 1 interface 0 interface 0 method _write vec3_1_0_0__write clock clks1_1 reset no_reset args {{{port vec3_1_0_0__write_1} {size 1}}} enable EN_vec3_1_0_0__write ready RDY_vec3_1_0_0__write method _read vec3_1_0_0__read clock no_clock reset no_reset args {} result vec3_1_0_0__read ready RDY_vec3_1_0_0__read interface 1 method _write vec3_1_0_1__write clock clks1_1 reset no_reset args {{{port vec3_1_0_1__write_1} {size 1}}} enable EN_vec3_1_0_1__write ready RDY_vec3_1_0_1__write method _read vec3_1_0_1__read clock no_clock reset no_reset args {} result vec3_1_0_1__read ready RDY_vec3_1_0_1__read interface 1 interface 0 method _write vec3_1_1_0__write clock clks1_1 reset no_reset args {{{port vec3_1_1_0__write_1} {size 1}}} enable EN_vec3_1_1_0__write ready RDY_vec3_1_1_0__write method _read vec3_1_1_0__read clock no_clock reset no_reset args {} result vec3_1_1_0__read ready RDY_vec3_1_1_0__read interface 1 method _write vec3_1_1_1__write clock clks1_1 reset no_reset args {{{port vec3_1_1_1__write_1} {size 1}}} enable EN_vec3_1_1_1__write ready RDY_vec3_1_1_1__write method _read vec3_1_1_1__read clock no_clock reset no_reset args {} result vec3_1_1_1__read ready RDY_vec3_1_1_1__read method data1 data1 clock no_clock reset no_reset args {} result data1 ready RDY_data1 method data2 data2 clock no_clock reset no_reset args {} result data2 ready RDY_data2 method data3 data3 clock no_clock reset no_reset args {} result data3 ready RDY_data3 interface clks1 interface 0 {clock {} clks1_0 {osc CLK_clks1_0} {gate CLK_GATE_clks1_0}} interface 1 {clock {} clks1_1 {osc CLK_clks1_1} {gate CLK_GATE_clks1_1}} interface rsts1 interface 0 {reset {} rsts1_0 {port RST_N_rsts1_0} {clock default_clock}} interface 1 {reset {} rsts1_1 {port RST_N_rsts1_1} {clock default_clock}} interface ios1 interface 0 {inout {} ios1_0 {port ios1_0} {clock clks1_1} {reset rsts1_1}} interface 1 {inout {} ios1_1 {port ios1_1} {clock clks1_1} {reset rsts1_1}} args inout io port io clock default_clock reset default_reset size 2 clock default_clock {osc CLK} reset default_reset port RST_N clock default_clock --------- Command: submodule ports mkM ptr RegN interface method _write _write clock _clk__1 reset _rst__1 args {{{port D_IN} {size 1}}} enable EN method _read _read clock _clk__1 reset _rst__1 args {} result Q_OUT args clock _clk__1 {osc CLK} reset _rst__1 {port RST} {clock _clk__1} parameter width {param width} parameter init {param init} r1 RegN interface method _write _write clock _clk__1 reset _rst__1 args {{{port D_IN} {size 1}}} enable EN method _read _read clock _clk__1 reset _rst__1 args {} result Q_OUT args clock _clk__1 {osc CLK} reset _rst__1 {port RST} {clock _clk__1} parameter width {param width} parameter init {param init} r2 RegN interface method _write _write clock _clk__1 reset _rst__1 args {{{port D_IN} {size 1}}} enable EN method _read _read clock _clk__1 reset _rst__1 args {} result Q_OUT args clock _clk__1 {osc CLK} reset _rst__1 {port RST} {clock _clk__1} parameter width {param width} parameter init {param init} --------- ---------- Command: submodule porttypes mkT r1 mkM ports CLK Clock RST_N Reset _write_1 Bool EN__write Bool RDY__write Bool _read Bool RDY__read Bool r2 mkM ports CLK Clock RST_N Reset _write_1 Bool EN__write Bool RDY__write Bool _read Bool RDY__read Bool mi mkI ports i Inout#(Test::Bar) CLK Clock RST_N Reset b Inout#(Test::Bar) mb VFoo ports V Int#(32) I_IN Inout#(Test::Bar) WVAL Bit#(4) WSET Bool WGET Bit#(4) WHAS Bool I_OUT Inout#(Bool) iv mkIfcWithVec ports io Inout#(Test::Bar) CLK Clock RST_N Reset vec1_0__write_1 Bool EN_vec1_0__write Bool RDY_vec1_0__write Bool vec1_0__read Bool RDY_vec1_0__read Bool vec1_1__write_1 Bool EN_vec1_1__write Bool RDY_vec1_1__write Bool vec1_1__read Bool RDY_vec1_1__read Bool vec2_0_0__write_1 Bool EN_vec2_0_0__write Bool RDY_vec2_0_0__write Bool vec2_0_0__read Bool RDY_vec2_0_0__read Bool vec2_0_1__write_1 Bool EN_vec2_0_1__write Bool RDY_vec2_0_1__write Bool vec2_0_1__read Bool RDY_vec2_0_1__read Bool vec2_1_0__write_1 Bool EN_vec2_1_0__write Bool RDY_vec2_1_0__write Bool vec2_1_0__read Bool RDY_vec2_1_0__read Bool vec2_1_1__write_1 Bool EN_vec2_1_1__write Bool RDY_vec2_1_1__write Bool vec2_1_1__read Bool RDY_vec2_1_1__read Bool vec3_0_0_0__write_1 Bool EN_vec3_0_0_0__write Bool RDY_vec3_0_0_0__write Bool vec3_0_0_0__read Bool RDY_vec3_0_0_0__read Bool vec3_0_0_1__write_1 Bool EN_vec3_0_0_1__write Bool RDY_vec3_0_0_1__write Bool vec3_0_0_1__read Bool RDY_vec3_0_0_1__read Bool vec3_0_1_0__write_1 Bool EN_vec3_0_1_0__write Bool RDY_vec3_0_1_0__write Bool vec3_0_1_0__read Bool RDY_vec3_0_1_0__read Bool vec3_0_1_1__write_1 Bool EN_vec3_0_1_1__write Bool RDY_vec3_0_1_1__write Bool vec3_0_1_1__read Bool RDY_vec3_0_1_1__read Bool vec3_1_0_0__write_1 Bool EN_vec3_1_0_0__write Bool RDY_vec3_1_0_0__write Bool vec3_1_0_0__read Bool RDY_vec3_1_0_0__read Bool vec3_1_0_1__write_1 Bool EN_vec3_1_0_1__write Bool RDY_vec3_1_0_1__write Bool vec3_1_0_1__read Bool RDY_vec3_1_0_1__read Bool vec3_1_1_0__write_1 Bool EN_vec3_1_1_0__write Bool RDY_vec3_1_1_0__write Bool vec3_1_1_0__read Bool RDY_vec3_1_1_0__read Bool vec3_1_1_1__write_1 Bool EN_vec3_1_1_1__write Bool RDY_vec3_1_1_1__write Bool vec3_1_1_1__read Bool RDY_vec3_1_1_1__read Bool data1 {Vector::Vector#(2, Bool)} RDY_data1 Bool data2 Vector::Vector#(2, Vector::Vector#(2, Bool)) RDY_data2 Bool data3 Vector::Vector#(2, Vector::Vector#(2, Vector::Vector#(2, Bool))) RDY_data3 Bool CLK_clks1_0 Clock CLK_GATE_clks1_0 Bool CLK_clks1_1 Clock CLK_GATE_clks1_1 Bool RST_N_rsts1_0 Reset RST_N_rsts1_1 Reset ios1_0 Inout#(Test::Bar) ios1_1 Inout#(Test::Bar) --------- Command: submodule porttypes mkM ptr RegN ports CLK Clock RST Reset D_IN Bool EN Bool Q_OUT Bool r1 RegN ports CLK Clock RST Reset D_IN Bool EN Bool Q_OUT Bool r2 RegN ports CLK Clock RST Reset D_IN Bool EN Bool Q_OUT Bool --------- ---------- Command: submodule full mkT r1 mkM ports CLK Clock RST_N Reset _write_1 Bool EN__write Bool RDY__write Bool _read Bool RDY__read Bool mports _write _write_1 _write EN__write RDY__write RDY__write _read _read RDY__read RDY__read position {Test.bsv 89 15} r2 mkM ports CLK Clock RST_N Reset _write_1 Bool EN__write Bool RDY__write Bool _read Bool RDY__read Bool mports _write _write_1 _write EN__write RDY__write RDY__write _read _read RDY__read RDY__read position {Test.bsv 90 15} mi mkI ports i Inout#(Test::Bar) CLK Clock RST_N Reset b Inout#(Test::Bar) mports {} position {Test.bsv 91 13} mb VFoo ports V Int#(32) I_IN Inout#(Test::Bar) WVAL Bit#(4) WSET Bool WGET Bit#(4) WHAS Bool I_OUT Inout#(Bool) mports {wset WVAL} {wset WSET} {whas WHAS} {wget WGET} position {Test.bsv 92 18} iv mkIfcWithVec ports io Inout#(Test::Bar) CLK Clock RST_N Reset vec1_0__write_1 Bool EN_vec1_0__write Bool RDY_vec1_0__write Bool vec1_0__read Bool RDY_vec1_0__read Bool vec1_1__write_1 Bool EN_vec1_1__write Bool RDY_vec1_1__write Bool vec1_1__read Bool RDY_vec1_1__read Bool vec2_0_0__write_1 Bool EN_vec2_0_0__write Bool RDY_vec2_0_0__write Bool vec2_0_0__read Bool RDY_vec2_0_0__read Bool vec2_0_1__write_1 Bool EN_vec2_0_1__write Bool RDY_vec2_0_1__write Bool vec2_0_1__read Bool RDY_vec2_0_1__read Bool vec2_1_0__write_1 Bool EN_vec2_1_0__write Bool RDY_vec2_1_0__write Bool vec2_1_0__read Bool RDY_vec2_1_0__read Bool vec2_1_1__write_1 Bool EN_vec2_1_1__write Bool RDY_vec2_1_1__write Bool vec2_1_1__read Bool RDY_vec2_1_1__read Bool vec3_0_0_0__write_1 Bool EN_vec3_0_0_0__write Bool RDY_vec3_0_0_0__write Bool vec3_0_0_0__read Bool RDY_vec3_0_0_0__read Bool vec3_0_0_1__write_1 Bool EN_vec3_0_0_1__write Bool RDY_vec3_0_0_1__write Bool vec3_0_0_1__read Bool RDY_vec3_0_0_1__read Bool vec3_0_1_0__write_1 Bool EN_vec3_0_1_0__write Bool RDY_vec3_0_1_0__write Bool vec3_0_1_0__read Bool RDY_vec3_0_1_0__read Bool vec3_0_1_1__write_1 Bool EN_vec3_0_1_1__write Bool RDY_vec3_0_1_1__write Bool vec3_0_1_1__read Bool RDY_vec3_0_1_1__read Bool vec3_1_0_0__write_1 Bool EN_vec3_1_0_0__write Bool RDY_vec3_1_0_0__write Bool vec3_1_0_0__read Bool RDY_vec3_1_0_0__read Bool vec3_1_0_1__write_1 Bool EN_vec3_1_0_1__write Bool RDY_vec3_1_0_1__write Bool vec3_1_0_1__read Bool RDY_vec3_1_0_1__read Bool vec3_1_1_0__write_1 Bool EN_vec3_1_1_0__write Bool RDY_vec3_1_1_0__write Bool vec3_1_1_0__read Bool RDY_vec3_1_1_0__read Bool vec3_1_1_1__write_1 Bool EN_vec3_1_1_1__write Bool RDY_vec3_1_1_1__write Bool vec3_1_1_1__read Bool RDY_vec3_1_1_1__read Bool data1 {Vector::Vector#(2, Bool)} RDY_data1 Bool data2 Vector::Vector#(2, Vector::Vector#(2, Bool)) RDY_data2 Bool data3 Vector::Vector#(2, Vector::Vector#(2, Vector::Vector#(2, Bool))) RDY_data3 Bool CLK_clks1_0 Clock CLK_GATE_clks1_0 Bool CLK_clks1_1 Clock CLK_GATE_clks1_1 Bool RST_N_rsts1_0 Reset RST_N_rsts1_1 Reset ios1_0 Inout#(Test::Bar) ios1_1 Inout#(Test::Bar) mports vec1_0__write vec1_0__write_1 vec1_0__write EN_vec1_0__write RDY_vec1_0__write RDY_vec1_0__write vec1_0__read vec1_0__read RDY_vec1_0__read RDY_vec1_0__read vec1_1__write vec1_1__write_1 vec1_1__write EN_vec1_1__write RDY_vec1_1__write RDY_vec1_1__write vec1_1__read vec1_1__read RDY_vec1_1__read RDY_vec1_1__read vec2_0_0__write vec2_0_0__write_1 vec2_0_0__write EN_vec2_0_0__write RDY_vec2_0_0__write RDY_vec2_0_0__write vec2_0_0__read vec2_0_0__read RDY_vec2_0_0__read RDY_vec2_0_0__read vec2_0_1__write vec2_0_1__write_1 vec2_0_1__write EN_vec2_0_1__write RDY_vec2_0_1__write RDY_vec2_0_1__write vec2_0_1__read vec2_0_1__read RDY_vec2_0_1__read RDY_vec2_0_1__read vec2_1_0__write vec2_1_0__write_1 vec2_1_0__write EN_vec2_1_0__write RDY_vec2_1_0__write RDY_vec2_1_0__write vec2_1_0__read vec2_1_0__read RDY_vec2_1_0__read RDY_vec2_1_0__read vec2_1_1__write vec2_1_1__write_1 vec2_1_1__write EN_vec2_1_1__write RDY_vec2_1_1__write RDY_vec2_1_1__write vec2_1_1__read vec2_1_1__read RDY_vec2_1_1__read RDY_vec2_1_1__read vec3_0_0_0__write vec3_0_0_0__write_1 vec3_0_0_0__write EN_vec3_0_0_0__write RDY_vec3_0_0_0__write RDY_vec3_0_0_0__write vec3_0_0_0__read vec3_0_0_0__read RDY_vec3_0_0_0__read RDY_vec3_0_0_0__read vec3_0_0_1__write vec3_0_0_1__write_1 vec3_0_0_1__write EN_vec3_0_0_1__write RDY_vec3_0_0_1__write RDY_vec3_0_0_1__write vec3_0_0_1__read vec3_0_0_1__read RDY_vec3_0_0_1__read RDY_vec3_0_0_1__read vec3_0_1_0__write vec3_0_1_0__write_1 vec3_0_1_0__write EN_vec3_0_1_0__write RDY_vec3_0_1_0__write RDY_vec3_0_1_0__write vec3_0_1_0__read vec3_0_1_0__read RDY_vec3_0_1_0__read RDY_vec3_0_1_0__read vec3_0_1_1__write vec3_0_1_1__write_1 vec3_0_1_1__write EN_vec3_0_1_1__write RDY_vec3_0_1_1__write RDY_vec3_0_1_1__write vec3_0_1_1__read vec3_0_1_1__read RDY_vec3_0_1_1__read RDY_vec3_0_1_1__read vec3_1_0_0__write vec3_1_0_0__write_1 vec3_1_0_0__write EN_vec3_1_0_0__write RDY_vec3_1_0_0__write RDY_vec3_1_0_0__write vec3_1_0_0__read vec3_1_0_0__read RDY_vec3_1_0_0__read RDY_vec3_1_0_0__read vec3_1_0_1__write vec3_1_0_1__write_1 vec3_1_0_1__write EN_vec3_1_0_1__write RDY_vec3_1_0_1__write RDY_vec3_1_0_1__write vec3_1_0_1__read vec3_1_0_1__read RDY_vec3_1_0_1__read RDY_vec3_1_0_1__read vec3_1_1_0__write vec3_1_1_0__write_1 vec3_1_1_0__write EN_vec3_1_1_0__write RDY_vec3_1_1_0__write RDY_vec3_1_1_0__write vec3_1_1_0__read vec3_1_1_0__read RDY_vec3_1_1_0__read RDY_vec3_1_1_0__read vec3_1_1_1__write vec3_1_1_1__write_1 vec3_1_1_1__write EN_vec3_1_1_1__write RDY_vec3_1_1_1__write RDY_vec3_1_1_1__write vec3_1_1_1__read vec3_1_1_1__read RDY_vec3_1_1_1__read RDY_vec3_1_1_1__read data1 data1 RDY_data1 RDY_data1 data2 data2 RDY_data2 RDY_data2 data3 data3 RDY_data3 RDY_data3 position {Test.bsv 93 15} --------- Command: submodule full mkM ptr RegN ports CLK Clock RST Reset D_IN Bool EN Bool Q_OUT Bool users {read {} _write {}} mports {{read Q_OUT} {write D_IN} {write EN}} position {Test.bsv 103 15} r1 RegN ports CLK Clock RST Reset D_IN Bool EN Bool Q_OUT Bool users read RL_rHello {RL_rWorld _read} {} write {} _write {} mports {{read Q_OUT} {write D_IN} {write EN}} position {Test.bsv 104 15} r2 RegN ports CLK Clock RST Reset D_IN Bool EN Bool Q_OUT Bool users read {} {RL_rWorld _read} {} write {} {_write RL_rWorld} {} mports {{read Q_OUT} {write D_IN} {write EN}} position {Test.bsv 105 15} --------- ----------