#!/usr/bin/perl
################################################################################

# USAGE: perl compareOutput.pl  mk<foo>.v  mk<verilogGeneratedBy ExpandPorts.tcl>.v

open(FL, $ARGV[0]) || die "can\'t open $ARGV[0]";

# open verilog output generated by bsc
while (<FL>) {
    s@//.*$@@;
    if (/^\s+(input|output).* ([\w_]+)\;$/) {
        $exp{$2} = 1;
    }
}
close FL;

############################################################
# open expected output we generated (wrapper file)
open(FL, $ARGV[1]) || die "can't open $ARGV[1]";
while (<FL>) {
    s@//.*$@@;
    if (/^\s*\.([\w_]+)/) {
        $wrapper{$1} = 1;
    }
}
close FL;

############################################################
# open expected output we generated (wrapper file)
open(FL, $ARGV[2]) || die "can't open $ARGV[2]";
while (<FL>) {
    s@//.*$@@;
    if (/^\s*\.([\w_]+)/) {
        $include{$1} = 1;
    }
}
close FL;

############################################################
$error = 0;
# now make sure everything exists in both files
foreach $item (sort keys %exp) {
    $pins++;
    if ($wrapper{$item} != 1) {
        print "ERROR: pin '$item' in $ARGV[0] but not $ARGV[1]\n";
        $error++;
     }
    if ($include{$item} != 1) {
        print "ERROR: pin '$item' in $ARGV[0] but not $ARGV[2]\n";
        $error++;
     }
}

foreach $item (sort keys %wrapper) {
    if ($exp{$item} != 1) {
        print "ERROR: pin '$item' in $ARGV[1] but not $ARGV[0]\n";
        $error++;
    }
}

foreach $item (sort keys %include) {
    if ($exp{$item} != 1) {
        print "ERROR: pin '$item' in $ARGV[2] but not $ARGV[0]\n";
        $error++;
    }
}

print "Info: $pins pins connected\n" ;

exit 1 if ($error != 0);

sub usage {
    print "USAGE: perl compareOutput.pl  mk<foo>.v  mk<verilogGeneratedBy ExpandPorts.tcl>.v\n";
    exit 1;
}