compile_verilog_pass_warning Vending0.bsv G0010 3

# Note: Bluesim executes system tasks at the posedge of clock,
# consistent with TRS semantics.  Verilog executes them at the
# negedge of clock, 1/2 cycle too early.  Until the Verilog
# behavior is changed, it is being given a separate expected file.

test_veri_only_bsv_modules TestVending {mkVending} sysTestVending.v.out.expected
test_c_only_bsv_modules TestVending {mkVending}