//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// read1                          O    32
// RDY_read1                      O     1 const
// read2                          O    32
// RDY_read2                      O     1 const
// RDY_write1                     O     1 const
// RDY_write2                     O     1 const
// CLK                            I     1 clock
// RST_N                          I     1 reset
// read1_addr                     I     4
// read2_addr                     I     4
// write1_addr                    I     4
// write1_data                    I    32 reg
// write2_addr                    I     4
// write2_data                    I    32 reg
// EN_write1                      I     1
// EN_write2                      I     1
//
// Combinational paths from inputs to outputs:
//   read1_addr -> read1
//   read2_addr -> read2
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkMulti(CLK,
	       RST_N,

	       read1_addr,
	       read1,
	       RDY_read1,

	       read2_addr,
	       read2,
	       RDY_read2,

	       write1_addr,
	       write1_data,
	       EN_write1,
	       RDY_write1,

	       write2_addr,
	       write2_data,
	       EN_write2,
	       RDY_write2);
  input  CLK;
  input  RST_N;

  // value method read1
  input  [3 : 0] read1_addr;
  output [31 : 0] read1;
  output RDY_read1;

  // value method read2
  input  [3 : 0] read2_addr;
  output [31 : 0] read2;
  output RDY_read2;

  // action method write1
  input  [3 : 0] write1_addr;
  input  [31 : 0] write1_data;
  input  EN_write1;
  output RDY_write1;

  // action method write2
  input  [3 : 0] write2_addr;
  input  [31 : 0] write2_data;
  input  EN_write2;
  output RDY_write2;

  // signals for module outputs
  wire [31 : 0] read1, read2;
  wire RDY_read1, RDY_read2, RDY_write1, RDY_write2;

  // register vec_0
  reg vec_0;
  wire vec_0$D_IN, vec_0$EN;

  // register vec_1
  reg vec_1;
  wire vec_1$D_IN, vec_1$EN;

  // register vec_10
  reg vec_10;
  wire vec_10$D_IN, vec_10$EN;

  // register vec_11
  reg vec_11;
  wire vec_11$D_IN, vec_11$EN;

  // register vec_12
  reg vec_12;
  wire vec_12$D_IN, vec_12$EN;

  // register vec_13
  reg vec_13;
  wire vec_13$D_IN, vec_13$EN;

  // register vec_14
  reg vec_14;
  wire vec_14$D_IN, vec_14$EN;

  // register vec_15
  reg vec_15;
  wire vec_15$D_IN, vec_15$EN;

  // register vec_2
  reg vec_2;
  wire vec_2$D_IN, vec_2$EN;

  // register vec_3
  reg vec_3;
  wire vec_3$D_IN, vec_3$EN;

  // register vec_4
  reg vec_4;
  wire vec_4$D_IN, vec_4$EN;

  // register vec_5
  reg vec_5;
  wire vec_5$D_IN, vec_5$EN;

  // register vec_6
  reg vec_6;
  wire vec_6$D_IN, vec_6$EN;

  // register vec_7
  reg vec_7;
  wire vec_7$D_IN, vec_7$EN;

  // register vec_8
  reg vec_8;
  wire vec_8$D_IN, vec_8$EN;

  // register vec_9
  reg vec_9;
  wire vec_9$D_IN, vec_9$EN;

  // ports of submodule rs_0
  wire [31 : 0] rs_0$D_IN, rs_0$D_OUT_1;
  wire [3 : 0] rs_0$ADDR_1,
	       rs_0$ADDR_2,
	       rs_0$ADDR_3,
	       rs_0$ADDR_4,
	       rs_0$ADDR_5,
	       rs_0$ADDR_IN;
  wire rs_0$WE;

  // ports of submodule rs_1
  wire [31 : 0] rs_1$D_IN, rs_1$D_OUT_1;
  wire [3 : 0] rs_1$ADDR_1,
	       rs_1$ADDR_2,
	       rs_1$ADDR_3,
	       rs_1$ADDR_4,
	       rs_1$ADDR_5,
	       rs_1$ADDR_IN;
  wire rs_1$WE;

  // ports of submodule rs_2
  wire [31 : 0] rs_2$D_IN, rs_2$D_OUT_1;
  wire [3 : 0] rs_2$ADDR_1,
	       rs_2$ADDR_2,
	       rs_2$ADDR_3,
	       rs_2$ADDR_4,
	       rs_2$ADDR_5,
	       rs_2$ADDR_IN;
  wire rs_2$WE;

  // ports of submodule rs_3
  wire [31 : 0] rs_3$D_IN, rs_3$D_OUT_1;
  wire [3 : 0] rs_3$ADDR_1,
	       rs_3$ADDR_2,
	       rs_3$ADDR_3,
	       rs_3$ADDR_4,
	       rs_3$ADDR_5,
	       rs_3$ADDR_IN;
  wire rs_3$WE;

  // inputs to muxes for submodule ports
  wire MUX_vec_0$write_1__SEL_1,
       MUX_vec_1$write_1__SEL_1,
       MUX_vec_10$write_1__SEL_1,
       MUX_vec_11$write_1__SEL_1,
       MUX_vec_12$write_1__SEL_1,
       MUX_vec_13$write_1__SEL_1,
       MUX_vec_14$write_1__SEL_1,
       MUX_vec_15$write_1__SEL_1,
       MUX_vec_2$write_1__SEL_1,
       MUX_vec_3$write_1__SEL_1,
       MUX_vec_4$write_1__SEL_1,
       MUX_vec_5$write_1__SEL_1,
       MUX_vec_6$write_1__SEL_1,
       MUX_vec_7$write_1__SEL_1,
       MUX_vec_8$write_1__SEL_1,
       MUX_vec_9$write_1__SEL_1;

  // remaining internal signals
  reg SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18,
      SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d21;

  // value method read1
  assign read1 =
	     SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18 ?
	       rs_2$D_OUT_1 :
	       rs_0$D_OUT_1 ;
  assign RDY_read1 = 1'd1 ;

  // value method read2
  assign read2 =
	     SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d21 ?
	       rs_3$D_OUT_1 :
	       rs_1$D_OUT_1 ;
  assign RDY_read2 = 1'd1 ;

  // action method write1
  assign RDY_write1 = 1'd1 ;

  // action method write2
  assign RDY_write2 = 1'd1 ;

  // submodule rs_0
  RegFile #(.addr_width(32'd4),
	    .data_width(32'd32),
	    .lo(4'h0),
	    .hi(4'd15)) rs_0(.CLK(CLK),
			     .ADDR_1(rs_0$ADDR_1),
			     .ADDR_2(rs_0$ADDR_2),
			     .ADDR_3(rs_0$ADDR_3),
			     .ADDR_4(rs_0$ADDR_4),
			     .ADDR_5(rs_0$ADDR_5),
			     .ADDR_IN(rs_0$ADDR_IN),
			     .D_IN(rs_0$D_IN),
			     .WE(rs_0$WE),
			     .D_OUT_1(rs_0$D_OUT_1),
			     .D_OUT_2(),
			     .D_OUT_3(),
			     .D_OUT_4(),
			     .D_OUT_5());

  // submodule rs_1
  RegFile #(.addr_width(32'd4),
	    .data_width(32'd32),
	    .lo(4'h0),
	    .hi(4'd15)) rs_1(.CLK(CLK),
			     .ADDR_1(rs_1$ADDR_1),
			     .ADDR_2(rs_1$ADDR_2),
			     .ADDR_3(rs_1$ADDR_3),
			     .ADDR_4(rs_1$ADDR_4),
			     .ADDR_5(rs_1$ADDR_5),
			     .ADDR_IN(rs_1$ADDR_IN),
			     .D_IN(rs_1$D_IN),
			     .WE(rs_1$WE),
			     .D_OUT_1(rs_1$D_OUT_1),
			     .D_OUT_2(),
			     .D_OUT_3(),
			     .D_OUT_4(),
			     .D_OUT_5());

  // submodule rs_2
  RegFile #(.addr_width(32'd4),
	    .data_width(32'd32),
	    .lo(4'h0),
	    .hi(4'd15)) rs_2(.CLK(CLK),
			     .ADDR_1(rs_2$ADDR_1),
			     .ADDR_2(rs_2$ADDR_2),
			     .ADDR_3(rs_2$ADDR_3),
			     .ADDR_4(rs_2$ADDR_4),
			     .ADDR_5(rs_2$ADDR_5),
			     .ADDR_IN(rs_2$ADDR_IN),
			     .D_IN(rs_2$D_IN),
			     .WE(rs_2$WE),
			     .D_OUT_1(rs_2$D_OUT_1),
			     .D_OUT_2(),
			     .D_OUT_3(),
			     .D_OUT_4(),
			     .D_OUT_5());

  // submodule rs_3
  RegFile #(.addr_width(32'd4),
	    .data_width(32'd32),
	    .lo(4'h0),
	    .hi(4'd15)) rs_3(.CLK(CLK),
			     .ADDR_1(rs_3$ADDR_1),
			     .ADDR_2(rs_3$ADDR_2),
			     .ADDR_3(rs_3$ADDR_3),
			     .ADDR_4(rs_3$ADDR_4),
			     .ADDR_5(rs_3$ADDR_5),
			     .ADDR_IN(rs_3$ADDR_IN),
			     .D_IN(rs_3$D_IN),
			     .WE(rs_3$WE),
			     .D_OUT_1(rs_3$D_OUT_1),
			     .D_OUT_2(),
			     .D_OUT_3(),
			     .D_OUT_4(),
			     .D_OUT_5());

  // inputs to muxes for submodule ports
  assign MUX_vec_0$write_1__SEL_1 = EN_write2 && write2_addr == 4'd0 ;
  assign MUX_vec_1$write_1__SEL_1 = EN_write2 && write2_addr == 4'd1 ;
  assign MUX_vec_10$write_1__SEL_1 = EN_write2 && write2_addr == 4'd10 ;
  assign MUX_vec_11$write_1__SEL_1 = EN_write2 && write2_addr == 4'd11 ;
  assign MUX_vec_12$write_1__SEL_1 = EN_write2 && write2_addr == 4'd12 ;
  assign MUX_vec_13$write_1__SEL_1 = EN_write2 && write2_addr == 4'd13 ;
  assign MUX_vec_14$write_1__SEL_1 = EN_write2 && write2_addr == 4'd14 ;
  assign MUX_vec_15$write_1__SEL_1 = EN_write2 && write2_addr == 4'd15 ;
  assign MUX_vec_2$write_1__SEL_1 = EN_write2 && write2_addr == 4'd2 ;
  assign MUX_vec_3$write_1__SEL_1 = EN_write2 && write2_addr == 4'd3 ;
  assign MUX_vec_4$write_1__SEL_1 = EN_write2 && write2_addr == 4'd4 ;
  assign MUX_vec_5$write_1__SEL_1 = EN_write2 && write2_addr == 4'd5 ;
  assign MUX_vec_6$write_1__SEL_1 = EN_write2 && write2_addr == 4'd6 ;
  assign MUX_vec_7$write_1__SEL_1 = EN_write2 && write2_addr == 4'd7 ;
  assign MUX_vec_8$write_1__SEL_1 = EN_write2 && write2_addr == 4'd8 ;
  assign MUX_vec_9$write_1__SEL_1 = EN_write2 && write2_addr == 4'd9 ;

  // register vec_0
  assign vec_0$D_IN = MUX_vec_0$write_1__SEL_1 ;
  assign vec_0$EN =
	     EN_write1 && write1_addr == 4'd0 ||
	     EN_write2 && write2_addr == 4'd0 ;

  // register vec_1
  assign vec_1$D_IN = MUX_vec_1$write_1__SEL_1 ;
  assign vec_1$EN =
	     EN_write1 && write1_addr == 4'd1 ||
	     EN_write2 && write2_addr == 4'd1 ;

  // register vec_10
  assign vec_10$D_IN = MUX_vec_10$write_1__SEL_1 ;
  assign vec_10$EN =
	     EN_write1 && write1_addr == 4'd10 ||
	     EN_write2 && write2_addr == 4'd10 ;

  // register vec_11
  assign vec_11$D_IN = MUX_vec_11$write_1__SEL_1 ;
  assign vec_11$EN =
	     EN_write1 && write1_addr == 4'd11 ||
	     EN_write2 && write2_addr == 4'd11 ;

  // register vec_12
  assign vec_12$D_IN = MUX_vec_12$write_1__SEL_1 ;
  assign vec_12$EN =
	     EN_write1 && write1_addr == 4'd12 ||
	     EN_write2 && write2_addr == 4'd12 ;

  // register vec_13
  assign vec_13$D_IN = MUX_vec_13$write_1__SEL_1 ;
  assign vec_13$EN =
	     EN_write1 && write1_addr == 4'd13 ||
	     EN_write2 && write2_addr == 4'd13 ;

  // register vec_14
  assign vec_14$D_IN = MUX_vec_14$write_1__SEL_1 ;
  assign vec_14$EN =
	     EN_write1 && write1_addr == 4'd14 ||
	     EN_write2 && write2_addr == 4'd14 ;

  // register vec_15
  assign vec_15$D_IN = MUX_vec_15$write_1__SEL_1 ;
  assign vec_15$EN =
	     EN_write1 && write1_addr == 4'd15 ||
	     EN_write2 && write2_addr == 4'd15 ;

  // register vec_2
  assign vec_2$D_IN = MUX_vec_2$write_1__SEL_1 ;
  assign vec_2$EN =
	     EN_write1 && write1_addr == 4'd2 ||
	     EN_write2 && write2_addr == 4'd2 ;

  // register vec_3
  assign vec_3$D_IN = MUX_vec_3$write_1__SEL_1 ;
  assign vec_3$EN =
	     EN_write1 && write1_addr == 4'd3 ||
	     EN_write2 && write2_addr == 4'd3 ;

  // register vec_4
  assign vec_4$D_IN = MUX_vec_4$write_1__SEL_1 ;
  assign vec_4$EN =
	     EN_write1 && write1_addr == 4'd4 ||
	     EN_write2 && write2_addr == 4'd4 ;

  // register vec_5
  assign vec_5$D_IN = MUX_vec_5$write_1__SEL_1 ;
  assign vec_5$EN =
	     EN_write1 && write1_addr == 4'd5 ||
	     EN_write2 && write2_addr == 4'd5 ;

  // register vec_6
  assign vec_6$D_IN = MUX_vec_6$write_1__SEL_1 ;
  assign vec_6$EN =
	     EN_write1 && write1_addr == 4'd6 ||
	     EN_write2 && write2_addr == 4'd6 ;

  // register vec_7
  assign vec_7$D_IN = MUX_vec_7$write_1__SEL_1 ;
  assign vec_7$EN =
	     EN_write1 && write1_addr == 4'd7 ||
	     EN_write2 && write2_addr == 4'd7 ;

  // register vec_8
  assign vec_8$D_IN = MUX_vec_8$write_1__SEL_1 ;
  assign vec_8$EN =
	     EN_write1 && write1_addr == 4'd8 ||
	     EN_write2 && write2_addr == 4'd8 ;

  // register vec_9
  assign vec_9$D_IN = MUX_vec_9$write_1__SEL_1 ;
  assign vec_9$EN =
	     EN_write1 && write1_addr == 4'd9 ||
	     EN_write2 && write2_addr == 4'd9 ;

  // submodule rs_0
  assign rs_0$ADDR_1 = read1_addr ;
  assign rs_0$ADDR_2 = 4'h0 ;
  assign rs_0$ADDR_3 = 4'h0 ;
  assign rs_0$ADDR_4 = 4'h0 ;
  assign rs_0$ADDR_5 = 4'h0 ;
  assign rs_0$ADDR_IN = write1_addr ;
  assign rs_0$D_IN = write1_data ;
  assign rs_0$WE = EN_write1 ;

  // submodule rs_1
  assign rs_1$ADDR_1 = read2_addr ;
  assign rs_1$ADDR_2 = 4'h0 ;
  assign rs_1$ADDR_3 = 4'h0 ;
  assign rs_1$ADDR_4 = 4'h0 ;
  assign rs_1$ADDR_5 = 4'h0 ;
  assign rs_1$ADDR_IN = write1_addr ;
  assign rs_1$D_IN = write1_data ;
  assign rs_1$WE = EN_write1 ;

  // submodule rs_2
  assign rs_2$ADDR_1 = read1_addr ;
  assign rs_2$ADDR_2 = 4'h0 ;
  assign rs_2$ADDR_3 = 4'h0 ;
  assign rs_2$ADDR_4 = 4'h0 ;
  assign rs_2$ADDR_5 = 4'h0 ;
  assign rs_2$ADDR_IN = write2_addr ;
  assign rs_2$D_IN = write2_data ;
  assign rs_2$WE = EN_write2 ;

  // submodule rs_3
  assign rs_3$ADDR_1 = read2_addr ;
  assign rs_3$ADDR_2 = 4'h0 ;
  assign rs_3$ADDR_3 = 4'h0 ;
  assign rs_3$ADDR_4 = 4'h0 ;
  assign rs_3$ADDR_5 = 4'h0 ;
  assign rs_3$ADDR_IN = write2_addr ;
  assign rs_3$D_IN = write2_data ;
  assign rs_3$WE = EN_write2 ;

  // remaining internal signals
  always@(read1_addr or
	  vec_0 or
	  vec_1 or
	  vec_2 or
	  vec_3 or
	  vec_4 or
	  vec_5 or
	  vec_6 or
	  vec_7 or
	  vec_8 or
	  vec_9 or vec_10 or vec_11 or vec_12 or vec_13 or vec_14 or vec_15)
  begin
    case (read1_addr)
      4'd0: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18 = vec_0;
      4'd1: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18 = vec_1;
      4'd2: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18 = vec_2;
      4'd3: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18 = vec_3;
      4'd4: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18 = vec_4;
      4'd5: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18 = vec_5;
      4'd6: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18 = vec_6;
      4'd7: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18 = vec_7;
      4'd8: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18 = vec_8;
      4'd9: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18 = vec_9;
      4'd10:
	  SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18 = vec_10;
      4'd11:
	  SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18 = vec_11;
      4'd12:
	  SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18 = vec_12;
      4'd13:
	  SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18 = vec_13;
      4'd14:
	  SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18 = vec_14;
      4'd15:
	  SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18 = vec_15;
    endcase
  end
  always@(read2_addr or
	  vec_0 or
	  vec_1 or
	  vec_2 or
	  vec_3 or
	  vec_4 or
	  vec_5 or
	  vec_6 or
	  vec_7 or
	  vec_8 or
	  vec_9 or vec_10 or vec_11 or vec_12 or vec_13 or vec_14 or vec_15)
  begin
    case (read2_addr)
      4'd0: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d21 = vec_0;
      4'd1: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d21 = vec_1;
      4'd2: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d21 = vec_2;
      4'd3: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d21 = vec_3;
      4'd4: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d21 = vec_4;
      4'd5: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d21 = vec_5;
      4'd6: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d21 = vec_6;
      4'd7: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d21 = vec_7;
      4'd8: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d21 = vec_8;
      4'd9: SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d21 = vec_9;
      4'd10:
	  SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d21 = vec_10;
      4'd11:
	  SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d21 = vec_11;
      4'd12:
	  SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d21 = vec_12;
      4'd13:
	  SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d21 = vec_13;
      4'd14:
	  SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d21 = vec_14;
      4'd15:
	  SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d21 = vec_15;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	vec_10 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	vec_11 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	vec_12 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	vec_13 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	vec_14 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	vec_15 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	vec_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	vec_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	vec_5 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	vec_6 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	vec_7 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	vec_8 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	vec_9 <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (vec_0$EN) vec_0 <= `BSV_ASSIGNMENT_DELAY vec_0$D_IN;
	if (vec_1$EN) vec_1 <= `BSV_ASSIGNMENT_DELAY vec_1$D_IN;
	if (vec_10$EN) vec_10 <= `BSV_ASSIGNMENT_DELAY vec_10$D_IN;
	if (vec_11$EN) vec_11 <= `BSV_ASSIGNMENT_DELAY vec_11$D_IN;
	if (vec_12$EN) vec_12 <= `BSV_ASSIGNMENT_DELAY vec_12$D_IN;
	if (vec_13$EN) vec_13 <= `BSV_ASSIGNMENT_DELAY vec_13$D_IN;
	if (vec_14$EN) vec_14 <= `BSV_ASSIGNMENT_DELAY vec_14$D_IN;
	if (vec_15$EN) vec_15 <= `BSV_ASSIGNMENT_DELAY vec_15$D_IN;
	if (vec_2$EN) vec_2 <= `BSV_ASSIGNMENT_DELAY vec_2$D_IN;
	if (vec_3$EN) vec_3 <= `BSV_ASSIGNMENT_DELAY vec_3$D_IN;
	if (vec_4$EN) vec_4 <= `BSV_ASSIGNMENT_DELAY vec_4$D_IN;
	if (vec_5$EN) vec_5 <= `BSV_ASSIGNMENT_DELAY vec_5$D_IN;
	if (vec_6$EN) vec_6 <= `BSV_ASSIGNMENT_DELAY vec_6$D_IN;
	if (vec_7$EN) vec_7 <= `BSV_ASSIGNMENT_DELAY vec_7$D_IN;
	if (vec_8$EN) vec_8 <= `BSV_ASSIGNMENT_DELAY vec_8$D_IN;
	if (vec_9$EN) vec_9 <= `BSV_ASSIGNMENT_DELAY vec_9$D_IN;
      end
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    vec_0 = 1'h0;
    vec_1 = 1'h0;
    vec_10 = 1'h0;
    vec_11 = 1'h0;
    vec_12 = 1'h0;
    vec_13 = 1'h0;
    vec_14 = 1'h0;
    vec_15 = 1'h0;
    vec_2 = 1'h0;
    vec_3 = 1'h0;
    vec_4 = 1'h0;
    vec_5 = 1'h0;
    vec_6 = 1'h0;
    vec_7 = 1'h0;
    vec_8 = 1'h0;
    vec_9 = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkMulti