//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 reset
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkTest(CLK,
	      RST_N);
  input  CLK;
  input  RST_N;

  // register p
  reg p;
  wire p$D_IN, p$EN;

  // ports of submodule f
  wire f$CLR, f$DEQ, f$D_IN, f$ENQ, f$FULL_N;

  // submodule f
  FIFOL1 #(.width(32'd1)) f(.RST(RST_N),
			    .CLK(CLK),
			    .D_IN(f$D_IN),
			    .ENQ(f$ENQ),
			    .DEQ(f$DEQ),
			    .CLR(f$CLR),
			    .D_OUT(),
			    .FULL_N(f$FULL_N),
			    .EMPTY_N());

  // register p
  assign p$D_IN = 1'd1 ;
  assign p$EN = f$FULL_N && p ;

  // submodule f
  assign f$D_IN = 1'd1 ;
  assign f$ENQ = f$FULL_N ;
  assign f$DEQ = 1'b0 ;
  assign f$CLR = 1'b0 ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (p$EN) p <= `BSV_ASSIGNMENT_DELAY p$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    p = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkTest