//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 reset
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkFOO(CLK,
	     RST_N);
  input  CLK;
  input  RST_N;

  // register addr
  reg [31 : 0] addr;
  wire [31 : 0] addr$D_IN;
  wire addr$EN;

  // register addr
  assign addr$D_IN = 32'h0 ;
  assign addr$EN = 1'b0 ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        addr <= `BSV_ASSIGNMENT_DELAY 32'hAAAAAAAA;
      end
    else
      begin
        if (addr$EN) addr <= `BSV_ASSIGNMENT_DELAY addr$D_IN;
      end
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    addr = 32'hAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE) if (addr[31:4] == 28'h0) $display("a");
    if (RST_N != `BSV_RESET_VALUE)
      if (addr[31:4] == 28'h0000001) $display("b");
    if (RST_N != `BSV_RESET_VALUE)
      if (addr[31:4] == 28'h0000002) $display("c");
    if (RST_N != `BSV_RESET_VALUE)
      if (addr[31:4] == 28'h0000048) $display("d");
    if (RST_N != `BSV_RESET_VALUE)
      if (addr[31:4] == 28'h0000480) $display("e");
    if (RST_N != `BSV_RESET_VALUE)
      if (addr[31:4] != 28'h0 && addr[31:4] != 28'h0000001 &&
	  addr[31:4] != 28'h0000002 &&
	  addr[31:4] != 28'h0000048 &&
	  addr[31:4] != 28'h0000480)
	$display("f");
  end
  // synopsys translate_on
endmodule  // mkFOO