//
// Generated by Bluespec Compiler
// 
//
// 
// Method conflict free info:
// [read CF write, [read, write] SB start]
// 
// Ports:
// Name                         I/O  size props
// read                           O     1 reg
// write                          O     1 reg
// clk                            I     1
// reset                          I     1 unused
// slowRam                        I     1
// EN_start                       I     1
// 
// No combinational paths from inputs to outputs
// 
//
module mkDesign(clk, reset, slowRam, EN_start, read, write);
  input  clk;
  input  reset;
  input  slowRam;
  input  EN_start;
  output read;
  output write;
  wire [1 : 0] currentState$D_IN,
	       currentState$Q_OUT,
	       nextState$D_IN,
	       nextState$Q_OUT;
  wire WILL_FIRE_RL_DELAY,
       WILL_FIRE_RL_READ,
       WILL_FIRE_RL_WRITE,
       currentState$EN,
       read,
       read_reg$D_IN,
       read_reg$EN,
       read_reg$Q_OUT,
       slowRam_reg$D_IN,
       slowRam_reg$EN,
       slowRam_reg$Q_OUT,
       write,
       write_reg$D_IN,
       write_reg$EN,
       write_reg$Q_OUT;

  RegUN #(.width(2)) currentState(.CLK(clk),
				  .D_IN(currentState$D_IN),
				  .EN(currentState$EN),
				  .Q_OUT(currentState$Q_OUT));

  RegUN #(.width(1)) read_reg(.CLK(clk),
			      .D_IN(read_reg$D_IN),
			      .EN(read_reg$EN),
			      .Q_OUT(read_reg$Q_OUT));

  RegUN #(.width(1)) slowRam_reg(.CLK(clk),
				 .D_IN(slowRam_reg$D_IN),
				 .EN(slowRam_reg$EN),
				 .Q_OUT(slowRam_reg$Q_OUT));

  RegUN #(.width(1)) write_reg(.CLK(clk),
			       .D_IN(write_reg$D_IN),
			       .EN(write_reg$EN),
			       .Q_OUT(write_reg$Q_OUT));

  assign WILL_FIRE_RL_DELAY = currentState$Q_OUT == 2'd2 ;
  assign WILL_FIRE_RL_READ = currentState$Q_OUT == 2'd0 ;
  assign WILL_FIRE_RL_WRITE = currentState$Q_OUT == 2'd1 ;
  assign currentState$D_IN =
	     {WILL_FIRE_RL_WRITE && slowRam_reg$Q_OUT,
	      WILL_FIRE_RL_READ} ;
  assign currentState$EN =
	     WILL_FIRE_RL_WRITE || WILL_FIRE_RL_DELAY ||
	     WILL_FIRE_RL_READ ;
  assign read = read_reg$Q_OUT ;
  assign read_reg$D_IN = WILL_FIRE_RL_READ ;
  assign read_reg$EN =
	     WILL_FIRE_RL_WRITE || WILL_FIRE_RL_DELAY ||
	     WILL_FIRE_RL_READ ;
  assign slowRam_reg$D_IN = slowRam ;
  assign slowRam_reg$EN = EN_start ;
  assign write = write_reg$Q_OUT ;
  assign write_reg$D_IN = WILL_FIRE_RL_WRITE ;
  assign write_reg$EN =
	     WILL_FIRE_RL_READ || WILL_FIRE_RL_DELAY ||
	     WILL_FIRE_RL_WRITE ;
endmodule  // mkDesign