//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 reset
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module sysBug262Opt(CLK,
		    RST_N);
  input  CLK;
  input  RST_N;

  // register done
  reg done;
  wire done$D_IN, done$EN;

  // register r
  reg [19 : 0] r;
  wire [19 : 0] r$D_IN;
  wire r$EN;

  // inputs to muxes for submodule ports
  wire [19 : 0] MUX_r$write_1__VAL_1;

  // inputs to muxes for submodule ports
  assign MUX_r$write_1__VAL_1 =
	     { 1'd0, 19'b0101010101010101010 /* unspecified value */  } ;

  // register done
  assign done$D_IN = 1'd1 ;
  assign done$EN = !done ;

  // register r
  assign r$D_IN = done ? MUX_r$write_1__VAL_1 : 20'd524293 ;
  assign r$EN = 1'b1 ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        done <= `BSV_ASSIGNMENT_DELAY 1'd0;
	r <= `BSV_ASSIGNMENT_DELAY
	    { 1'd0, 19'b0101010101010101010 /* unspecified value */  };
      end
    else
      begin
        if (done$EN) done <= `BSV_ASSIGNMENT_DELAY done$D_IN;
	if (r$EN) r <= `BSV_ASSIGNMENT_DELAY r$D_IN;
      end
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    done = 1'h0;
    r = 20'hAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE) if (done) $finish(32'd0);
  end
  // synopsys translate_on
endmodule  // sysBug262Opt