//
// Generated by Bluespec Compiler
// 
// 
// Ports:
// Name                         I/O  size props
// RDY_calc                       O     1 const
// result                         O     1 reg
// RDY_result                     O     1 const
// CLK                            I     1 clock
// RST_N                          I     1 reset
// calc_x                         I     1
// calc_y                         I     1
// EN_calc                        I     1
// 
// No combinational paths from inputs to outputs
// 
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkDesign_in(CLK,
		   RST_N,
		   
		   calc_x,
		   calc_y,
		   EN_calc,
		   RDY_calc,
		   
		   result,
		   RDY_result);
  input  CLK;
  input  RST_N;
  
  // action method calc
  input  calc_x;
  input  calc_y;
  input  EN_calc;
  output RDY_calc;
  
  // value method result
  output result;
  output RDY_result;

  // signals for module outputs
  wire RDY_calc, RDY_result, result;

  // register i_sum
  reg i_sum;
  wire i_sum$D_IN, i_sum$EN;

  // action method calc
  assign RDY_calc = 1'd1 ;

  // value method result
  assign result = i_sum ;
  assign RDY_result = 1'd1 ;

  // register i_sum
  assign i_sum$D_IN = calc_x + calc_y ;
  assign i_sum$EN = EN_calc ;

  // handling of inlined registers
  
  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        i_sum <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (i_sum$EN) i_sum <= `BSV_ASSIGNMENT_DELAY i_sum$D_IN;
      end
  end
  
  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    i_sum = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkDesign_in