//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 reset
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module top(CLK,
	   RST_N);
  input  CLK;
  input  RST_N;

  // ports of submodule foo
  wire foo$EN_calc, foo$calc_x, foo$calc_y;

  // submodule foo
  mkDesign_in foo(.CLK(CLK),
		  .RST_N(RST_N),
		  .calc_x(foo$calc_x),
		  .calc_y(foo$calc_y),
		  .EN_calc(foo$EN_calc),
		  .RDY_calc(),
		  .result(),
		  .RDY_result());

  // submodule foo
  assign foo$calc_x = 1'b0 ;
  assign foo$calc_y = 1'b0 ;
  assign foo$EN_calc = 1'b0 ;
endmodule  // top