//
// Generated by Bluespec Compiler
//
// 
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 reset
// 
// No combinational paths from inputs to outputs
// 
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module top2(CLK,
	    RST_N);
  input  CLK;
  input  RST_N;

  // ports of submodule foo
  wire foo$calc_aa, foo$calc_ab, foo$calc_ba, foo$calc_bb;

  // submodule foo
  mkDesign foo(.clk(CLK),
	       .reset(RST_N),
	       .calc_aa(foo$calc_aa),
	       .calc_ab(foo$calc_ab),
	       .calc_ba(foo$calc_ba),
	       .calc_bb(foo$calc_bb),
	       .result_adder1(),
	       .result_adder2());

  // submodule foo
  assign foo$calc_aa = 1'd1 ;
  assign foo$calc_ab = 1'd1 ;
  assign foo$calc_ba = 1'd1 ;
  assign foo$calc_bb = 1'd1 ;
endmodule  // top2