//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// done                           O     1 reg
// product                        O     8 reg
// clk                            I     1 clock
// reset                          I     1 reset
// shift_and_add_a                I     4 reg
// shift_and_add_b                I     4 reg
// shift_and_add_load             I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkDesign1(clk,
		 reset,

		 shift_and_add_a,
		 shift_and_add_b,
		 shift_and_add_load,

		 done,

		 product);
  input  clk;
  input  reset;

  // action method shift_and_add
  input  [3 : 0] shift_and_add_a;
  input  [3 : 0] shift_and_add_b;
  input  shift_and_add_load;

  // value method done
  output done;

  // value method product
  output [7 : 0] product;

  // signals for module outputs
  wire [7 : 0] product;
  wire done;

  // register accumulator
  reg [7 : 0] accumulator;
  wire [7 : 0] accumulator$D_IN;
  wire accumulator$EN;

  // register count
  reg [3 : 0] count;
  wire [3 : 0] count$D_IN;
  wire count$EN;

  // register done_reg
  reg done_reg;
  wire done_reg$D_IN, done_reg$EN;

  // register enable
  reg enable;
  wire enable$D_IN, enable$EN;

  // register multiplicand
  reg [7 : 0] multiplicand;
  wire [7 : 0] multiplicand$D_IN;
  wire multiplicand$EN;

  // register multiplier
  reg [3 : 0] multiplier;
  wire [3 : 0] multiplier$D_IN;
  wire multiplier$EN;

  // inputs to muxes for submodule ports
  wire [7 : 0] MUX_multiplicand$write_1__VAL_1;
  wire MUX_accumulator$write_1__SEL_1;

  // value method done
  assign done = done_reg ;

  // value method product
  assign product = accumulator ;

  // inputs to muxes for submodule ports
  assign MUX_accumulator$write_1__SEL_1 =
	     shift_and_add_load && count == 4'd0 ;
  assign MUX_multiplicand$write_1__VAL_1 = { 4'b0, shift_and_add_a } ;

  // register accumulator
  assign accumulator$D_IN = 8'd0 ;
  assign accumulator$EN = MUX_accumulator$write_1__SEL_1 ;

  // register count
  assign count$D_IN = 4'd0 ;
  assign count$EN = 1'b1 ;

  // register done_reg
  assign done_reg$D_IN = 1'd1 ;
  assign done_reg$EN = 1'b1 ;

  // register enable
  assign enable$D_IN = 1'd0 ;
  assign enable$EN = 1'b1 ;

  // register multiplicand
  assign multiplicand$D_IN = MUX_multiplicand$write_1__VAL_1 ;
  assign multiplicand$EN = MUX_accumulator$write_1__SEL_1 ;

  // register multiplier
  assign multiplier$D_IN = shift_and_add_b ;
  assign multiplier$EN = MUX_accumulator$write_1__SEL_1 ;

  // handling of inlined registers

  always@(posedge clk)
  begin
    if (reset == `BSV_RESET_VALUE)
      begin
        accumulator <= `BSV_ASSIGNMENT_DELAY 8'd0;
	count <= `BSV_ASSIGNMENT_DELAY 4'd0;
	done_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	enable <= `BSV_ASSIGNMENT_DELAY 1'd0;
	multiplicand <= `BSV_ASSIGNMENT_DELAY 8'd0;
	multiplier <= `BSV_ASSIGNMENT_DELAY 4'd0;
      end
    else
      begin
        if (accumulator$EN)
	  accumulator <= `BSV_ASSIGNMENT_DELAY accumulator$D_IN;
	if (count$EN) count <= `BSV_ASSIGNMENT_DELAY count$D_IN;
	if (done_reg$EN) done_reg <= `BSV_ASSIGNMENT_DELAY done_reg$D_IN;
	if (enable$EN) enable <= `BSV_ASSIGNMENT_DELAY enable$D_IN;
	if (multiplicand$EN)
	  multiplicand <= `BSV_ASSIGNMENT_DELAY multiplicand$D_IN;
	if (multiplier$EN)
	  multiplier <= `BSV_ASSIGNMENT_DELAY multiplier$D_IN;
      end
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    accumulator = 8'hAA;
    count = 4'hA;
    done_reg = 1'h0;
    enable = 1'h0;
    multiplicand = 8'hAA;
    multiplier = 4'hA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkDesign1