//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// result                         O    11
// clk                            I     1 unused
// reset                          I     1 unused
// result_a                       I    10
// result_b                       I     5
//
// Combinational paths from inputs to outputs:
//   (result_a, result_b) -> result
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkDesign(clk,
		reset,

		result_a,
		result_b,
		result);
  input  clk;
  input  reset;

  // value method result
  input  [9 : 0] result_a;
  input  [4 : 0] result_b;
  output [10 : 0] result;

  // signals for module outputs
  wire [10 : 0] result;

  // remaining internal signals
  wire [5 : 0] _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d55,
	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d56,
	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d57,
	       _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d58,
	       _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d59,
	       x__h144,
	       x__h146,
	       x__h240,
	       x__h242,
	       x__h336,
	       x__h338,
	       x__h432,
	       x__h434,
	       x__h528,
	       x__h530,
	       y__h147;
  wire [4 : 0] IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d54,
	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC__q4,
	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC___d53,
	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC__q3,
	       IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC___d52,
	       IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC__q2,
	       IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC___d51,
	       IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC__q1,
	       _theResult_____1_snd__h939,
	       notB__h48,
	       quotient__h63;

  // value method result
  assign result =
	     { result_a[9:5] >= result_b,
	       _theResult_____1_snd__h939,
	       quotient__h63 } ;

  // remaining internal signals
  assign IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d54 =
	     { IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC__q4[3:0],
	       result_a[0] } ;
  assign IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC__q4 =
	     _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d56[5] ?
	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d56[4:0] :
	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC___d53 ;
  assign IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC___d53 =
	     { IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC__q3[3:0],
	       result_a[1] } ;
  assign IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC__q3 =
	     _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d57[5] ?
	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d57[4:0] :
	       IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC___d52 ;
  assign IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC___d52 =
	     { IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC__q2[3:0],
	       result_a[2] } ;
  assign IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC__q2 =
	     _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d58[5] ?
	       _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d58[4:0] :
	       IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC___d51 ;
  assign IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC___d51 =
	     { IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC__q1[3:0],
	       result_a[3] } ;
  assign IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC__q1 =
	     _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d59[5] ?
	       _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d59[4:0] :
	       result_a[8:4] ;
  assign _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d55 =
	     x__h144 + 6'd1 ;
  assign _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d56 =
	     x__h240 + 6'd1 ;
  assign _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d57 =
	     x__h336 + 6'd1 ;
  assign _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d58 =
	     x__h432 + 6'd1 ;
  assign _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d59 =
	     x__h528 + 6'd1 ;
  assign _theResult_____1_snd__h939 =
	     _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d55[5] ?
	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d55[4:0] :
	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d54 ;
  assign notB__h48 = ~result_b ;
  assign quotient__h63 =
	     { _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d59[5],
	       _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d58[5],
	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d57[5],
	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d56[5],
	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d55[5] } ;
  assign x__h144 = x__h146 + y__h147 ;
  assign x__h146 =
	     { 1'd0,
	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d54 } ;
  assign x__h240 = x__h242 + y__h147 ;
  assign x__h242 =
	     { 1'd0,
	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC___d53 } ;
  assign x__h336 = x__h338 + y__h147 ;
  assign x__h338 =
	     { 1'd0,
	       IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC___d52 } ;
  assign x__h432 = x__h434 + y__h147 ;
  assign x__h434 =
	     { 1'd0,
	       IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC___d51 } ;
  assign x__h528 = x__h530 + y__h147 ;
  assign x__h530 = { 1'd0, result_a[8:4] } ;
  assign y__h147 = { 1'd0, notB__h48 } ;
endmodule  // mkDesign