//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 reset
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkTest(CLK,
	      RST_N);
  input  CLK;
  input  RST_N;

  // register the_cnd
  reg [2 : 0] the_cnd;
  wire [2 : 0] the_cnd$D_IN;
  wire the_cnd$EN;

  // register the_y
  reg [3 : 0] the_y;
  reg [3 : 0] the_y$D_IN;
  wire the_y$EN;

  // register the_cnd
  assign the_cnd$D_IN = 3'h0 ;
  assign the_cnd$EN = 1'b0 ;

  // register the_y
  always@(the_cnd)
  begin
    case (1'b1) // synopsys parallel_case
      the_cnd == 3'd1: the_y$D_IN = 4'd1;
      the_cnd == 3'd0: the_y$D_IN = 4'd2;
      the_cnd == 3'd2: the_y$D_IN = 4'd4;
      default: the_y$D_IN = 4'b1010 /* unspecified value */ ;
    endcase
  end
  assign the_y$EN = the_cnd == 3'd1 || the_cnd == 3'd0 || the_cnd == 3'd2 ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        the_cnd <= `BSV_ASSIGNMENT_DELAY 3'd4;
	the_y <= `BSV_ASSIGNMENT_DELAY 4'd0;
      end
    else
      begin
        if (the_cnd$EN) the_cnd <= `BSV_ASSIGNMENT_DELAY the_cnd$D_IN;
	if (the_y$EN) the_y <= `BSV_ASSIGNMENT_DELAY the_y$D_IN;
      end
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    the_cnd = 3'h2;
    the_y = 4'hA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkTest