//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// start                          O    32
// RDY_start                      O     1 const
// CLK                            I     1 unused
// RST_N                          I     1 unused
// start_a                        I    32
// start_b                        I    32
// start_c                        I     1
//
// Combinational paths from inputs to outputs:
//   (start_a, start_b, start_c) -> start
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkAddSub(CLK,
		RST_N,

		start_a,
		start_b,
		start_c,
		start,
		RDY_start);
  input  CLK;
  input  RST_N;

  // value method start
  input  [31 : 0] start_a;
  input  [31 : 0] start_b;
  input  start_c;
  output [31 : 0] start;
  output RDY_start;

  // signals for module outputs
  wire [31 : 0] start;
  wire RDY_start;

  // remaining internal signals
  wire [31 : 0] b_in__h23;

  // value method start
  assign start = start_a + b_in__h23 ;
  assign RDY_start = 1'd1 ;

  // remaining internal signals
  assign b_in__h23 = start_c ? start_b : ~start_b + 32'd1 ;
endmodule  // mkAddSub