//
// Generated by Bluespec Compiler
//
// 
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 reset
// 
// No combinational paths from inputs to outputs
// 
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module tb(CLK,
	  RST_N);
  input  CLK;
  input  RST_N;

  // ports of submodule dut
  wire [31 : 0] dut$start, dut$start_a, dut$start_b;
  wire dut$start_c;

  // submodule dut
  mkAddSub dut(.CLK(CLK),
	       .RST_N(RST_N),
	       .start_a(dut$start_a),
	       .start_b(dut$start_b),
	       .start_c(dut$start_c),
	       .start(dut$start),
	       .RDY_start());

  // submodule dut
  assign dut$start_a = 32'd5 ;
  assign dut$start_b = 32'd6 ;
  assign dut$start_c = 1'd1 ;

  // handling of system tasks
  
  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    $display("5+6=%d", dut$start);
    $finish(32'd0);
  end
  // synopsys translate_on
endmodule  // tb