//
// Generated by Bluespec Compiler
//
// Method conflict free info:
// [deq CF enq,
//  enq CF first,
//  [deq, enq] SB clear,
//  first SB [clear, deq]]
// 
// Ports:
// Name                         I/O  size props
// RDY_enq                        O     1
// RDY_deq                        O     1
// first                          O    32 reg
// RDY_first                      O     1
// RDY_clear                      O     1 const
// CLK                            I     1
// RST_N                          I     1
// enq_1                          I    32
// EN_enq                         I     1
// EN_deq                         I     1
// EN_clear                       I     1
// 
// No combinational paths from inputs to outputs
// 
//
module sysFIFOPush(CLK,
		   RST_N,
		   enq_1,
		   EN_enq,
		   EN_deq,
		   EN_clear,
		   RDY_enq,
		   RDY_deq,
		   first,
		   RDY_first,
		   RDY_clear);
  input  CLK;
  input  RST_N;
  input  [31 : 0] enq_1;
  input  EN_enq;
  input  EN_deq;
  input  EN_clear;
  output RDY_enq;
  output RDY_deq;
  output [31 : 0] first;
  output RDY_first;
  output RDY_clear;
  wire [31 : 0] a$D_IN, a$D_OUT, b$D_IN, b$D_OUT, first;
  wire RDY_clear,
       RDY_deq,
       RDY_enq,
       RDY_first,
       WILL_FIRE_RL_push,
       a$CLR,
       a$DEQ,
       a$ENQ,
       a$FULL_N,
       b$CLR,
       b$DEQ,
       b$ENQ,
       b$FULL_N;

  FIFO2 #(.width(32)) a(.CLK(CLK),
			.CLK_GATE(1'd1),
			.RST_N(RST_N),
			.D_IN(a$D_IN),
			.ENQ(a$ENQ),
			.FULL_N(a$FULL_N),
			.DEQ(a$DEQ),
			.D_OUT(a$D_OUT),
			.CLR(a$CLR));

  FIFO2 #(.width(32)) b(.CLK(CLK),
			.CLK_GATE(1'd1),
			.RST_N(RST_N),
			.D_IN(b$D_IN),
			.ENQ(b$ENQ),
			.FULL_N(b$FULL_N),
			.DEQ(b$DEQ),
			.D_OUT(b$D_OUT),
			.CLR(b$CLR));

  assign RDY_clear = 1'd1 ;
  assign RDY_deq = b$FULL_N ;
  assign RDY_enq = a$FULL_N ;
  assign RDY_first = b$FULL_N ;
  assign WILL_FIRE_RL_push =
	     b$FULL_N && a$FULL_N ;
  assign a$CLR = EN_clear ;
  assign a$DEQ = WILL_FIRE_RL_push ;
  assign a$D_IN = enq_1 ;
  assign a$ENQ = EN_enq ;
  assign b$CLR = EN_clear ;
  assign b$DEQ = EN_deq ;
  assign b$D_IN = a$D_OUT ;
  assign b$ENQ = WILL_FIRE_RL_push ;
  assign first = b$D_OUT ;
endmodule  // sysFIFOPush