//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// CLK_clocks_0                   O     1
// CLK_GATE_clocks_0              O     1 const
// CLK_clocks_1                   O     1
// CLK_GATE_clocks_1              O     1 const
// CLK_clocks_2                   O     1
// CLK_GATE_clocks_2              O     1 const
// CLK_in_clocks_0                I     1
// CLK_in_clocks_1                I     1
// CLK_in_clocks_2                I     1
// CLK                            I     1 unused
// RST_N                          I     1 unused
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkClockListNPassThrough(CLK_in_clocks_0,
			       CLK_in_clocks_1,
			       CLK_in_clocks_2,
			       CLK,
			       RST_N,

			       CLK_clocks_0,
			       CLK_GATE_clocks_0,

			       CLK_clocks_1,
			       CLK_GATE_clocks_1,

			       CLK_clocks_2,
			       CLK_GATE_clocks_2);
  input  CLK_in_clocks_0;
  input  CLK_in_clocks_1;
  input  CLK_in_clocks_2;
  input  CLK;
  input  RST_N;

  // oscillator and gates for output clock CLK_clocks_0
  output CLK_clocks_0;
  output CLK_GATE_clocks_0;

  // oscillator and gates for output clock CLK_clocks_1
  output CLK_clocks_1;
  output CLK_GATE_clocks_1;

  // oscillator and gates for output clock CLK_clocks_2
  output CLK_clocks_2;
  output CLK_GATE_clocks_2;

  // signals for module outputs
  wire CLK_GATE_clocks_0,
       CLK_GATE_clocks_1,
       CLK_GATE_clocks_2,
       CLK_clocks_0,
       CLK_clocks_1,
       CLK_clocks_2;

  // oscillator and gates for output clock CLK_clocks_0
  assign CLK_clocks_0 = CLK_in_clocks_0 ;
  assign CLK_GATE_clocks_0 = 1'd1 ;

  // oscillator and gates for output clock CLK_clocks_1
  assign CLK_clocks_1 = CLK_in_clocks_1 ;
  assign CLK_GATE_clocks_1 = 1'd1 ;

  // oscillator and gates for output clock CLK_clocks_2
  assign CLK_clocks_2 = CLK_in_clocks_2 ;
  assign CLK_GATE_clocks_2 = 1'd1 ;
endmodule  // mkClockListNPassThrough