//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 reset
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module sysUserGuide_RegInsts(CLK,
			     RST_N);
  input  CLK;
  input  RST_N;

  // register reg_1
  reg [50 : 0] reg_1;
  wire [50 : 0] reg_1$D_IN;
  wire reg_1$EN;

  // register reg_2
  reg [50 : 0] reg_2;
  wire [50 : 0] reg_2$D_IN;
  wire reg_2$EN;

  // register reg_3
  reg [50 : 0] reg_3;
  wire [50 : 0] reg_3$D_IN;
  wire reg_3$EN;

  // register reg_1
  assign reg_1$D_IN = 51'h0 ;
  assign reg_1$EN = 1'b0 ;

  // register reg_2
  assign reg_2$D_IN = 51'h0 ;
  assign reg_2$EN = 1'b0 ;

  // register reg_3
  assign reg_3$D_IN = 51'h0 ;
  assign reg_3$EN = 1'b0 ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        reg_1 <= `BSV_ASSIGNMENT_DELAY 51'd0;
      end
    else
      begin
        if (reg_1$EN) reg_1 <= `BSV_ASSIGNMENT_DELAY reg_1$D_IN;
      end
    if (reg_2$EN) reg_2 <= `BSV_ASSIGNMENT_DELAY reg_2$D_IN;
  end

  always@(posedge CLK or `BSV_RESET_EDGE RST_N)
  if (RST_N == `BSV_RESET_VALUE)
    begin
      reg_3 <= `BSV_ASSIGNMENT_DELAY 51'd0;
    end
  else
    begin
      if (reg_3$EN) reg_3 <= `BSV_ASSIGNMENT_DELAY reg_3$D_IN;
    end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    reg_1 = 51'h2AAAAAAAAAAAA;
    reg_2 = 51'h2AAAAAAAAAAAA;
    reg_3 = 51'h2AAAAAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // sysUserGuide_RegInsts