// // Generated by Bluespec Compiler // // // Ports: // Name I/O size props // CLK I 1 clock // RST_N I 1 reset // // No combinational paths from inputs to outputs // // `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif `ifdef BSV_POSITIVE_RESET `define BSV_RESET_VALUE 1'b1 `define BSV_RESET_EDGE posedge `else `define BSV_RESET_VALUE 1'b0 `define BSV_RESET_EDGE negedge `endif module mkWhenCurry(CLK, RST_N); input CLK; input RST_N; // register pred1 reg pred1; wire pred1$D_IN, pred1$EN; // register pred2 reg pred2; wire pred2$D_IN, pred2$EN; // register switch reg switch; wire switch$D_IN, switch$EN; // rule scheduling signals wire WILL_FIRE_RL_go; // rule RL_go assign WILL_FIRE_RL_go = switch ? pred1 : pred2 ; // register pred1 assign pred1$D_IN = 1'b0 ; assign pred1$EN = 1'b0 ; // register pred2 assign pred2$D_IN = 1'b0 ; assign pred2$EN = 1'b0 ; // register switch assign switch$D_IN = 1'b0 ; assign switch$EN = 1'b0 ; // handling of inlined registers always@(posedge CLK) begin if (RST_N == `BSV_RESET_VALUE) begin pred1 <= `BSV_ASSIGNMENT_DELAY 1'd1; pred2 <= `BSV_ASSIGNMENT_DELAY 1'd1; switch <= `BSV_ASSIGNMENT_DELAY 1'd0; end else begin if (pred1$EN) pred1 <= `BSV_ASSIGNMENT_DELAY pred1$D_IN; if (pred2$EN) pred2 <= `BSV_ASSIGNMENT_DELAY pred2$D_IN; if (switch$EN) switch <= `BSV_ASSIGNMENT_DELAY switch$D_IN; end end // synopsys translate_off `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS initial begin pred1 = 1'h0; pred2 = 1'h0; switch = 1'h0; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on // handling of system tasks // synopsys translate_off always@(negedge CLK) begin #0; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_go) $display($signed(switch ? 32'd6 : 32'd7)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_go) $finish(32'd0); end // synopsys translate_on endmodule // mkWhenCurry