//
// Generated by Bluespec Compiler
//
// 
// Ports:
// Name                         I/O  size props
// test                           O     1 reg
// RDY_test                       O     1 const
// CLK                            I     1 clock
// RST_N                          I     1 reset
// 
// No combinational paths from inputs to outputs
// 
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkLTEMinusOne(CLK,
		     RST_N,
		     
		     test,
		     RDY_test);
  input  CLK;
  input  RST_N;
  
  // value method test
  output test;
  output RDY_test;

  // signals for module outputs
  wire RDY_test, test;

  // register r
  reg [20 : 0] r;
  wire [20 : 0] r$D_IN;
  wire r$EN;

  // value method test
  assign test = r[20] ;
  assign RDY_test = 1'd1 ;

  // register r
  assign r$D_IN = 21'h0 ;
  assign r$EN = 1'b0 ;

  // handling of inlined registers
  
  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        r <= `BSV_ASSIGNMENT_DELAY 21'd2097151;
      end
    else
      begin
        if (r$EN) r <= `BSV_ASSIGNMENT_DELAY r$D_IN;
      end
  end
  
  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    r = 21'h0AAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkLTEMinusOne