//
// Generated by Bluespec Compiler
//
// 
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 unused
// 
// No combinational paths from inputs to outputs
// 
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkReplaceBitOpt(CLK,
		       RST_N);
  input  CLK;
  input  RST_N;

  // register r
  reg [2047 : 0] r;
  wire [2047 : 0] r$D_IN;
  wire r$EN;

  // register s
  reg s;
  wire s$D_IN, s$EN;

  // register r
  assign r$D_IN = { r[2047:1025], s, r[1023:0] } ;
  assign r$EN = 1'd1 ;

  // register s
  assign s$D_IN = 1'b0 ;
  assign s$EN = 1'b0 ;

  // handling of inlined registers
  
  always@(posedge CLK)
  begin
    if (r$EN) r <= `BSV_ASSIGNMENT_DELAY r$D_IN;
    if (s$EN) s <= `BSV_ASSIGNMENT_DELAY s$D_IN;
  end
  
  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    r = 2048'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    s = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkReplaceBitOpt