//
// Generated by Bluespec Compiler
//
// 
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 unused
// 
// No combinational paths from inputs to outputs
// 
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkShiftBit1(CLK,
		   RST_N);
  input  CLK;
  input  RST_N;

  // register sl
  reg sl;
  wire sl$D_IN, sl$EN;

  // register sra
  reg sra;
  wire sra$D_IN, sra$EN;

  // register srl
  reg srl;
  wire srl$D_IN, srl$EN;

  // register x
  reg x;
  wire x$D_IN, x$EN;

  // register y
  reg [14 : 0] y;
  wire [14 : 0] y$D_IN;
  wire y$EN;

  // register sl
  assign sl$D_IN = y == 15'd0 && x ;
  assign sl$EN = 1'd1 ;

  // register sra
  assign sra$D_IN = x ;
  assign sra$EN = 1'd1 ;

  // register srl
  assign srl$D_IN = y == 15'd0 && x ;
  assign srl$EN = 1'd1 ;

  // register x
  assign x$D_IN = 1'b0 ;
  assign x$EN = 1'b0 ;

  // register y
  assign y$D_IN = 15'h0 ;
  assign y$EN = 1'b0 ;

  // handling of inlined registers
  
  always@(posedge CLK)
  begin
    if (sl$EN) sl <= `BSV_ASSIGNMENT_DELAY sl$D_IN;
    if (sra$EN) sra <= `BSV_ASSIGNMENT_DELAY sra$D_IN;
    if (srl$EN) srl <= `BSV_ASSIGNMENT_DELAY srl$D_IN;
    if (x$EN) x <= `BSV_ASSIGNMENT_DELAY x$D_IN;
    if (y$EN) y <= `BSV_ASSIGNMENT_DELAY y$D_IN;
  end
  
  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    sl = 1'h0;
    sra = 1'h0;
    srl = 1'h0;
    x = 1'h0;
    y = 15'h2AAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkShiftBit1