//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// out                            O     7
// RDY_out                        O     1 const
// CLK                            I     1 clock
// RST_N                          I     1 unused
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module sysITransformConcatIf(CLK,
			     RST_N,

			     out,
			     RDY_out);
  input  CLK;
  input  RST_N;

  // value method out
  output [6 : 0] out;
  output RDY_out;

  // signals for module outputs
  wire [6 : 0] out;
  wire RDY_out;

  // register a
  reg [2 : 0] a;
  wire [2 : 0] a$D_IN;
  wire a$EN;

  // register b
  reg [2 : 0] b;
  wire [2 : 0] b$D_IN;
  wire b$EN;

  // register c
  reg [3 : 0] c;
  wire [3 : 0] c$D_IN;
  wire c$EN;

  // register cond
  reg cond;
  wire cond$D_IN, cond$EN;

  // register d
  reg [3 : 0] d;
  wire [3 : 0] d$D_IN;
  wire d$EN;

  // value method out
  assign out = cond ? { a, c } : { b, d } ;
  assign RDY_out = 1'd1 ;

  // register a
  assign a$D_IN = 3'h0 ;
  assign a$EN = 1'b0 ;

  // register b
  assign b$D_IN = 3'h0 ;
  assign b$EN = 1'b0 ;

  // register c
  assign c$D_IN = 4'h0 ;
  assign c$EN = 1'b0 ;

  // register cond
  assign cond$D_IN = 1'b0 ;
  assign cond$EN = 1'b0 ;

  // register d
  assign d$D_IN = 4'h0 ;
  assign d$EN = 1'b0 ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (a$EN) a <= `BSV_ASSIGNMENT_DELAY a$D_IN;
    if (b$EN) b <= `BSV_ASSIGNMENT_DELAY b$D_IN;
    if (c$EN) c <= `BSV_ASSIGNMENT_DELAY c$D_IN;
    if (cond$EN) cond <= `BSV_ASSIGNMENT_DELAY cond$D_IN;
    if (d$EN) d <= `BSV_ASSIGNMENT_DELAY d$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    a = 3'h2;
    b = 3'h2;
    c = 4'hA;
    cond = 1'h0;
    d = 4'hA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // sysITransformConcatIf