// // Generated by Bluespec Compiler // // // Ports: // Name I/O size props // CLK I 1 clock // RST_N I 1 reset // // No combinational paths from inputs to outputs // // `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif `ifdef BSV_POSITIVE_RESET `define BSV_RESET_VALUE 1'b1 `define BSV_RESET_EDGE posedge `else `define BSV_RESET_VALUE 1'b0 `define BSV_RESET_EDGE negedge `endif module sysArrayReg3D(CLK, RST_N); input CLK; input RST_N; // register i reg [7 : 0] i; wire [7 : 0] i$D_IN; wire i$EN; // register j reg [7 : 0] j; wire [7 : 0] j$D_IN; wire j$EN; // register k reg [7 : 0] k; wire [7 : 0] k$D_IN; wire k$EN; // register r3_0_0_0 reg [7 : 0] r3_0_0_0; wire [7 : 0] r3_0_0_0$D_IN; wire r3_0_0_0$EN; // register r3_0_0_1 reg [7 : 0] r3_0_0_1; wire [7 : 0] r3_0_0_1$D_IN; wire r3_0_0_1$EN; // register r3_0_0_2 reg [7 : 0] r3_0_0_2; wire [7 : 0] r3_0_0_2$D_IN; wire r3_0_0_2$EN; // register r3_0_0_3 reg [7 : 0] r3_0_0_3; wire [7 : 0] r3_0_0_3$D_IN; wire r3_0_0_3$EN; // register r3_0_1_0 reg [7 : 0] r3_0_1_0; wire [7 : 0] r3_0_1_0$D_IN; wire r3_0_1_0$EN; // register r3_0_1_1 reg [7 : 0] r3_0_1_1; wire [7 : 0] r3_0_1_1$D_IN; wire r3_0_1_1$EN; // register r3_0_1_2 reg [7 : 0] r3_0_1_2; wire [7 : 0] r3_0_1_2$D_IN; wire r3_0_1_2$EN; // register r3_0_1_3 reg [7 : 0] r3_0_1_3; wire [7 : 0] r3_0_1_3$D_IN; wire r3_0_1_3$EN; // register r3_0_2_0 reg [7 : 0] r3_0_2_0; wire [7 : 0] r3_0_2_0$D_IN; wire r3_0_2_0$EN; // register r3_0_2_1 reg [7 : 0] r3_0_2_1; wire [7 : 0] r3_0_2_1$D_IN; wire r3_0_2_1$EN; // register r3_0_2_2 reg [7 : 0] r3_0_2_2; wire [7 : 0] r3_0_2_2$D_IN; wire r3_0_2_2$EN; // register r3_0_2_3 reg [7 : 0] r3_0_2_3; wire [7 : 0] r3_0_2_3$D_IN; wire r3_0_2_3$EN; // register r3_0_3_0 reg [7 : 0] r3_0_3_0; wire [7 : 0] r3_0_3_0$D_IN; wire r3_0_3_0$EN; // register r3_0_3_1 reg [7 : 0] r3_0_3_1; wire [7 : 0] r3_0_3_1$D_IN; wire r3_0_3_1$EN; // register r3_0_3_2 reg [7 : 0] r3_0_3_2; wire [7 : 0] r3_0_3_2$D_IN; wire r3_0_3_2$EN; // register r3_0_3_3 reg [7 : 0] r3_0_3_3; wire [7 : 0] r3_0_3_3$D_IN; wire r3_0_3_3$EN; // register r3_1_0_0 reg [7 : 0] r3_1_0_0; wire [7 : 0] r3_1_0_0$D_IN; wire r3_1_0_0$EN; // register r3_1_0_1 reg [7 : 0] r3_1_0_1; wire [7 : 0] r3_1_0_1$D_IN; wire r3_1_0_1$EN; // register r3_1_0_2 reg [7 : 0] r3_1_0_2; wire [7 : 0] r3_1_0_2$D_IN; wire r3_1_0_2$EN; // register r3_1_0_3 reg [7 : 0] r3_1_0_3; wire [7 : 0] r3_1_0_3$D_IN; wire r3_1_0_3$EN; // register r3_1_1_0 reg [7 : 0] r3_1_1_0; wire [7 : 0] r3_1_1_0$D_IN; wire r3_1_1_0$EN; // register r3_1_1_1 reg [7 : 0] r3_1_1_1; wire [7 : 0] r3_1_1_1$D_IN; wire r3_1_1_1$EN; // register r3_1_1_2 reg [7 : 0] r3_1_1_2; wire [7 : 0] r3_1_1_2$D_IN; wire r3_1_1_2$EN; // register r3_1_1_3 reg [7 : 0] r3_1_1_3; wire [7 : 0] r3_1_1_3$D_IN; wire r3_1_1_3$EN; // register r3_1_2_0 reg [7 : 0] r3_1_2_0; wire [7 : 0] r3_1_2_0$D_IN; wire r3_1_2_0$EN; // register r3_1_2_1 reg [7 : 0] r3_1_2_1; wire [7 : 0] r3_1_2_1$D_IN; wire r3_1_2_1$EN; // register r3_1_2_2 reg [7 : 0] r3_1_2_2; wire [7 : 0] r3_1_2_2$D_IN; wire r3_1_2_2$EN; // register r3_1_2_3 reg [7 : 0] r3_1_2_3; wire [7 : 0] r3_1_2_3$D_IN; wire r3_1_2_3$EN; // register r3_1_3_0 reg [7 : 0] r3_1_3_0; wire [7 : 0] r3_1_3_0$D_IN; wire r3_1_3_0$EN; // register r3_1_3_1 reg [7 : 0] r3_1_3_1; wire [7 : 0] r3_1_3_1$D_IN; wire r3_1_3_1$EN; // register r3_1_3_2 reg [7 : 0] r3_1_3_2; wire [7 : 0] r3_1_3_2$D_IN; wire r3_1_3_2$EN; // register r3_1_3_3 reg [7 : 0] r3_1_3_3; wire [7 : 0] r3_1_3_3$D_IN; wire r3_1_3_3$EN; // register r3_2_0_0 reg [7 : 0] r3_2_0_0; wire [7 : 0] r3_2_0_0$D_IN; wire r3_2_0_0$EN; // register r3_2_0_1 reg [7 : 0] r3_2_0_1; wire [7 : 0] r3_2_0_1$D_IN; wire r3_2_0_1$EN; // register r3_2_0_2 reg [7 : 0] r3_2_0_2; wire [7 : 0] r3_2_0_2$D_IN; wire r3_2_0_2$EN; // register r3_2_0_3 reg [7 : 0] r3_2_0_3; wire [7 : 0] r3_2_0_3$D_IN; wire r3_2_0_3$EN; // register r3_2_1_0 reg [7 : 0] r3_2_1_0; wire [7 : 0] r3_2_1_0$D_IN; wire r3_2_1_0$EN; // register r3_2_1_1 reg [7 : 0] r3_2_1_1; wire [7 : 0] r3_2_1_1$D_IN; wire r3_2_1_1$EN; // register r3_2_1_2 reg [7 : 0] r3_2_1_2; wire [7 : 0] r3_2_1_2$D_IN; wire r3_2_1_2$EN; // register r3_2_1_3 reg [7 : 0] r3_2_1_3; wire [7 : 0] r3_2_1_3$D_IN; wire r3_2_1_3$EN; // register r3_2_2_0 reg [7 : 0] r3_2_2_0; wire [7 : 0] r3_2_2_0$D_IN; wire r3_2_2_0$EN; // register r3_2_2_1 reg [7 : 0] r3_2_2_1; wire [7 : 0] r3_2_2_1$D_IN; wire r3_2_2_1$EN; // register r3_2_2_2 reg [7 : 0] r3_2_2_2; wire [7 : 0] r3_2_2_2$D_IN; wire r3_2_2_2$EN; // register r3_2_2_3 reg [7 : 0] r3_2_2_3; wire [7 : 0] r3_2_2_3$D_IN; wire r3_2_2_3$EN; // register r3_2_3_0 reg [7 : 0] r3_2_3_0; wire [7 : 0] r3_2_3_0$D_IN; wire r3_2_3_0$EN; // register r3_2_3_1 reg [7 : 0] r3_2_3_1; wire [7 : 0] r3_2_3_1$D_IN; wire r3_2_3_1$EN; // register r3_2_3_2 reg [7 : 0] r3_2_3_2; wire [7 : 0] r3_2_3_2$D_IN; wire r3_2_3_2$EN; // register r3_2_3_3 reg [7 : 0] r3_2_3_3; wire [7 : 0] r3_2_3_3$D_IN; wire r3_2_3_3$EN; // register r3_3_0_0 reg [7 : 0] r3_3_0_0; wire [7 : 0] r3_3_0_0$D_IN; wire r3_3_0_0$EN; // register r3_3_0_1 reg [7 : 0] r3_3_0_1; wire [7 : 0] r3_3_0_1$D_IN; wire r3_3_0_1$EN; // register r3_3_0_2 reg [7 : 0] r3_3_0_2; wire [7 : 0] r3_3_0_2$D_IN; wire r3_3_0_2$EN; // register r3_3_0_3 reg [7 : 0] r3_3_0_3; wire [7 : 0] r3_3_0_3$D_IN; wire r3_3_0_3$EN; // register r3_3_1_0 reg [7 : 0] r3_3_1_0; wire [7 : 0] r3_3_1_0$D_IN; wire r3_3_1_0$EN; // register r3_3_1_1 reg [7 : 0] r3_3_1_1; wire [7 : 0] r3_3_1_1$D_IN; wire r3_3_1_1$EN; // register r3_3_1_2 reg [7 : 0] r3_3_1_2; wire [7 : 0] r3_3_1_2$D_IN; wire r3_3_1_2$EN; // register r3_3_1_3 reg [7 : 0] r3_3_1_3; wire [7 : 0] r3_3_1_3$D_IN; wire r3_3_1_3$EN; // register r3_3_2_0 reg [7 : 0] r3_3_2_0; wire [7 : 0] r3_3_2_0$D_IN; wire r3_3_2_0$EN; // register r3_3_2_1 reg [7 : 0] r3_3_2_1; wire [7 : 0] r3_3_2_1$D_IN; wire r3_3_2_1$EN; // register r3_3_2_2 reg [7 : 0] r3_3_2_2; wire [7 : 0] r3_3_2_2$D_IN; wire r3_3_2_2$EN; // register r3_3_2_3 reg [7 : 0] r3_3_2_3; wire [7 : 0] r3_3_2_3$D_IN; wire r3_3_2_3$EN; // register r3_3_3_0 reg [7 : 0] r3_3_3_0; wire [7 : 0] r3_3_3_0$D_IN; wire r3_3_3_0$EN; // register r3_3_3_1 reg [7 : 0] r3_3_3_1; wire [7 : 0] r3_3_3_1$D_IN; wire r3_3_3_1$EN; // register r3_3_3_2 reg [7 : 0] r3_3_3_2; wire [7 : 0] r3_3_3_2$D_IN; wire r3_3_3_2$EN; // register r3_3_3_3 reg [7 : 0] r3_3_3_3; wire [7 : 0] r3_3_3_3$D_IN; wire r3_3_3_3$EN; // rule scheduling signals wire WILL_FIRE_RL_tick, WILL_FIRE_RL_write; // remaining internal signals reg [7 : 0] SEL_ARR_SEL_ARR_SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_ETC___d187, SEL_ARR_SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_0_2_0_r_ETC___d154, SEL_ARR_SEL_ARR_r3_1_0_0_2_r3_1_0_1_4_r3_1_0_2_ETC___d164, SEL_ARR_SEL_ARR_r3_2_0_0_7_r3_2_0_1_9_r3_2_0_2_ETC___d174, SEL_ARR_SEL_ARR_r3_3_0_0_11_r3_3_0_1_13_r3_3_0_ETC___d184, SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_0_2_0_r3_0_0_3__ETC___d145, SEL_ARR_r3_0_1_0_5_r3_0_1_1_7_r3_0_1_2_9_r3_0__ETC___d147, SEL_ARR_r3_0_2_0_3_r3_0_2_1_5_r3_0_2_2_7_r3_0__ETC___d149, SEL_ARR_r3_0_3_0_3_r3_0_3_1_5_r3_0_3_2_7_r3_0__ETC___d151, SEL_ARR_r3_1_0_0_2_r3_1_0_1_4_r3_1_0_2_6_r3_1__ETC___d156, SEL_ARR_r3_1_1_0_0_r3_1_1_1_2_r3_1_1_2_4_r3_1__ETC___d158, SEL_ARR_r3_1_2_0_8_r3_1_2_1_0_r3_1_2_2_2_r3_1__ETC___d160, SEL_ARR_r3_1_3_0_8_r3_1_3_1_0_r3_1_3_2_2_r3_1__ETC___d162, SEL_ARR_r3_2_0_0_7_r3_2_0_1_9_r3_2_0_2_1_r3_2__ETC___d166, SEL_ARR_r3_2_1_0_5_r3_2_1_1_7_r3_2_1_2_9_r3_2__ETC___d168, SEL_ARR_r3_2_2_0_3_r3_2_2_1_5_r3_2_2_2_7_r3_2__ETC___d170, SEL_ARR_r3_2_3_0_02_r3_2_3_1_04_r3_2_3_2_06_r3_ETC___d172, SEL_ARR_r3_3_0_0_11_r3_3_0_1_13_r3_3_0_2_15_r3_ETC___d176, SEL_ARR_r3_3_1_0_19_r3_3_1_1_21_r3_3_1_2_23_r3_ETC___d178, SEL_ARR_r3_3_2_0_27_r3_3_2_1_29_r3_3_2_2_31_r3_ETC___d180, SEL_ARR_r3_3_3_0_35_r3_3_3_1_37_r3_3_3_2_39_r3_ETC___d182; wire [15 : 0] j_53_MUL_k___d202; // rule RL_write assign WILL_FIRE_RL_write = i < 8'd4 && j < 8'd4 && k < 8'd4 ; // rule RL_tick assign WILL_FIRE_RL_tick = k < 8'd4 ; // register i assign i$D_IN = (i == 8'd3) ? 8'd0 : i + 8'd1 ; assign i$EN = WILL_FIRE_RL_tick ; // register j assign j$D_IN = (j == 8'd3) ? 8'd0 : j + 8'd1 ; assign j$EN = WILL_FIRE_RL_tick && i == 8'd3 ; // register k assign k$D_IN = k + 8'd1 ; assign k$EN = WILL_FIRE_RL_tick && i == 8'd3 && j == 8'd3 ; // register r3_0_0_0 assign r3_0_0_0$D_IN = i + j_53_MUL_k___d202[7:0] ; assign r3_0_0_0$EN = WILL_FIRE_RL_write && k == 8'd0 && j == 8'd0 && i == 8'd0 ; // register r3_0_0_1 assign r3_0_0_1$D_IN = r3_0_0_0$D_IN ; assign r3_0_0_1$EN = WILL_FIRE_RL_write && k == 8'd1 && j == 8'd0 && i == 8'd0 ; // register r3_0_0_2 assign r3_0_0_2$D_IN = r3_0_0_0$D_IN ; assign r3_0_0_2$EN = WILL_FIRE_RL_write && k == 8'd2 && j == 8'd0 && i == 8'd0 ; // register r3_0_0_3 assign r3_0_0_3$D_IN = r3_0_0_0$D_IN ; assign r3_0_0_3$EN = WILL_FIRE_RL_write && k == 8'd3 && j == 8'd0 && i == 8'd0 ; // register r3_0_1_0 assign r3_0_1_0$D_IN = r3_0_0_0$D_IN ; assign r3_0_1_0$EN = WILL_FIRE_RL_write && k == 8'd0 && j == 8'd1 && i == 8'd0 ; // register r3_0_1_1 assign r3_0_1_1$D_IN = r3_0_0_0$D_IN ; assign r3_0_1_1$EN = WILL_FIRE_RL_write && k == 8'd1 && j == 8'd1 && i == 8'd0 ; // register r3_0_1_2 assign r3_0_1_2$D_IN = r3_0_0_0$D_IN ; assign r3_0_1_2$EN = WILL_FIRE_RL_write && k == 8'd2 && j == 8'd1 && i == 8'd0 ; // register r3_0_1_3 assign r3_0_1_3$D_IN = r3_0_0_0$D_IN ; assign r3_0_1_3$EN = WILL_FIRE_RL_write && k == 8'd3 && j == 8'd1 && i == 8'd0 ; // register r3_0_2_0 assign r3_0_2_0$D_IN = r3_0_0_0$D_IN ; assign r3_0_2_0$EN = WILL_FIRE_RL_write && k == 8'd0 && j == 8'd2 && i == 8'd0 ; // register r3_0_2_1 assign r3_0_2_1$D_IN = r3_0_0_0$D_IN ; assign r3_0_2_1$EN = WILL_FIRE_RL_write && k == 8'd1 && j == 8'd2 && i == 8'd0 ; // register r3_0_2_2 assign r3_0_2_2$D_IN = r3_0_0_0$D_IN ; assign r3_0_2_2$EN = WILL_FIRE_RL_write && k == 8'd2 && j == 8'd2 && i == 8'd0 ; // register r3_0_2_3 assign r3_0_2_3$D_IN = r3_0_0_0$D_IN ; assign r3_0_2_3$EN = WILL_FIRE_RL_write && k == 8'd3 && j == 8'd2 && i == 8'd0 ; // register r3_0_3_0 assign r3_0_3_0$D_IN = r3_0_0_0$D_IN ; assign r3_0_3_0$EN = WILL_FIRE_RL_write && k == 8'd0 && j == 8'd3 && i == 8'd0 ; // register r3_0_3_1 assign r3_0_3_1$D_IN = r3_0_0_0$D_IN ; assign r3_0_3_1$EN = WILL_FIRE_RL_write && k == 8'd1 && j == 8'd3 && i == 8'd0 ; // register r3_0_3_2 assign r3_0_3_2$D_IN = r3_0_0_0$D_IN ; assign r3_0_3_2$EN = WILL_FIRE_RL_write && k == 8'd2 && j == 8'd3 && i == 8'd0 ; // register r3_0_3_3 assign r3_0_3_3$D_IN = r3_0_0_0$D_IN ; assign r3_0_3_3$EN = WILL_FIRE_RL_write && k == 8'd3 && j == 8'd3 && i == 8'd0 ; // register r3_1_0_0 assign r3_1_0_0$D_IN = r3_0_0_0$D_IN ; assign r3_1_0_0$EN = WILL_FIRE_RL_write && k == 8'd0 && j == 8'd0 && i == 8'd1 ; // register r3_1_0_1 assign r3_1_0_1$D_IN = r3_0_0_0$D_IN ; assign r3_1_0_1$EN = WILL_FIRE_RL_write && k == 8'd1 && j == 8'd0 && i == 8'd1 ; // register r3_1_0_2 assign r3_1_0_2$D_IN = r3_0_0_0$D_IN ; assign r3_1_0_2$EN = WILL_FIRE_RL_write && k == 8'd2 && j == 8'd0 && i == 8'd1 ; // register r3_1_0_3 assign r3_1_0_3$D_IN = r3_0_0_0$D_IN ; assign r3_1_0_3$EN = WILL_FIRE_RL_write && k == 8'd3 && j == 8'd0 && i == 8'd1 ; // register r3_1_1_0 assign r3_1_1_0$D_IN = r3_0_0_0$D_IN ; assign r3_1_1_0$EN = WILL_FIRE_RL_write && k == 8'd0 && j == 8'd1 && i == 8'd1 ; // register r3_1_1_1 assign r3_1_1_1$D_IN = r3_0_0_0$D_IN ; assign r3_1_1_1$EN = WILL_FIRE_RL_write && k == 8'd1 && j == 8'd1 && i == 8'd1 ; // register r3_1_1_2 assign r3_1_1_2$D_IN = r3_0_0_0$D_IN ; assign r3_1_1_2$EN = WILL_FIRE_RL_write && k == 8'd2 && j == 8'd1 && i == 8'd1 ; // register r3_1_1_3 assign r3_1_1_3$D_IN = r3_0_0_0$D_IN ; assign r3_1_1_3$EN = WILL_FIRE_RL_write && k == 8'd3 && j == 8'd1 && i == 8'd1 ; // register r3_1_2_0 assign r3_1_2_0$D_IN = r3_0_0_0$D_IN ; assign r3_1_2_0$EN = WILL_FIRE_RL_write && k == 8'd0 && j == 8'd2 && i == 8'd1 ; // register r3_1_2_1 assign r3_1_2_1$D_IN = r3_0_0_0$D_IN ; assign r3_1_2_1$EN = WILL_FIRE_RL_write && k == 8'd1 && j == 8'd2 && i == 8'd1 ; // register r3_1_2_2 assign r3_1_2_2$D_IN = r3_0_0_0$D_IN ; assign r3_1_2_2$EN = WILL_FIRE_RL_write && k == 8'd2 && j == 8'd2 && i == 8'd1 ; // register r3_1_2_3 assign r3_1_2_3$D_IN = r3_0_0_0$D_IN ; assign r3_1_2_3$EN = WILL_FIRE_RL_write && k == 8'd3 && j == 8'd2 && i == 8'd1 ; // register r3_1_3_0 assign r3_1_3_0$D_IN = r3_0_0_0$D_IN ; assign r3_1_3_0$EN = WILL_FIRE_RL_write && k == 8'd0 && j == 8'd3 && i == 8'd1 ; // register r3_1_3_1 assign r3_1_3_1$D_IN = r3_0_0_0$D_IN ; assign r3_1_3_1$EN = WILL_FIRE_RL_write && k == 8'd1 && j == 8'd3 && i == 8'd1 ; // register r3_1_3_2 assign r3_1_3_2$D_IN = r3_0_0_0$D_IN ; assign r3_1_3_2$EN = WILL_FIRE_RL_write && k == 8'd2 && j == 8'd3 && i == 8'd1 ; // register r3_1_3_3 assign r3_1_3_3$D_IN = r3_0_0_0$D_IN ; assign r3_1_3_3$EN = WILL_FIRE_RL_write && k == 8'd3 && j == 8'd3 && i == 8'd1 ; // register r3_2_0_0 assign r3_2_0_0$D_IN = r3_0_0_0$D_IN ; assign r3_2_0_0$EN = WILL_FIRE_RL_write && k == 8'd0 && j == 8'd0 && i == 8'd2 ; // register r3_2_0_1 assign r3_2_0_1$D_IN = r3_0_0_0$D_IN ; assign r3_2_0_1$EN = WILL_FIRE_RL_write && k == 8'd1 && j == 8'd0 && i == 8'd2 ; // register r3_2_0_2 assign r3_2_0_2$D_IN = r3_0_0_0$D_IN ; assign r3_2_0_2$EN = WILL_FIRE_RL_write && k == 8'd2 && j == 8'd0 && i == 8'd2 ; // register r3_2_0_3 assign r3_2_0_3$D_IN = r3_0_0_0$D_IN ; assign r3_2_0_3$EN = WILL_FIRE_RL_write && k == 8'd3 && j == 8'd0 && i == 8'd2 ; // register r3_2_1_0 assign r3_2_1_0$D_IN = r3_0_0_0$D_IN ; assign r3_2_1_0$EN = WILL_FIRE_RL_write && k == 8'd0 && j == 8'd1 && i == 8'd2 ; // register r3_2_1_1 assign r3_2_1_1$D_IN = r3_0_0_0$D_IN ; assign r3_2_1_1$EN = WILL_FIRE_RL_write && k == 8'd1 && j == 8'd1 && i == 8'd2 ; // register r3_2_1_2 assign r3_2_1_2$D_IN = r3_0_0_0$D_IN ; assign r3_2_1_2$EN = WILL_FIRE_RL_write && k == 8'd2 && j == 8'd1 && i == 8'd2 ; // register r3_2_1_3 assign r3_2_1_3$D_IN = r3_0_0_0$D_IN ; assign r3_2_1_3$EN = WILL_FIRE_RL_write && k == 8'd3 && j == 8'd1 && i == 8'd2 ; // register r3_2_2_0 assign r3_2_2_0$D_IN = r3_0_0_0$D_IN ; assign r3_2_2_0$EN = WILL_FIRE_RL_write && k == 8'd0 && j == 8'd2 && i == 8'd2 ; // register r3_2_2_1 assign r3_2_2_1$D_IN = r3_0_0_0$D_IN ; assign r3_2_2_1$EN = WILL_FIRE_RL_write && k == 8'd1 && j == 8'd2 && i == 8'd2 ; // register r3_2_2_2 assign r3_2_2_2$D_IN = r3_0_0_0$D_IN ; assign r3_2_2_2$EN = WILL_FIRE_RL_write && k == 8'd2 && j == 8'd2 && i == 8'd2 ; // register r3_2_2_3 assign r3_2_2_3$D_IN = r3_0_0_0$D_IN ; assign r3_2_2_3$EN = WILL_FIRE_RL_write && k == 8'd3 && j == 8'd2 && i == 8'd2 ; // register r3_2_3_0 assign r3_2_3_0$D_IN = r3_0_0_0$D_IN ; assign r3_2_3_0$EN = WILL_FIRE_RL_write && k == 8'd0 && j == 8'd3 && i == 8'd2 ; // register r3_2_3_1 assign r3_2_3_1$D_IN = r3_0_0_0$D_IN ; assign r3_2_3_1$EN = WILL_FIRE_RL_write && k == 8'd1 && j == 8'd3 && i == 8'd2 ; // register r3_2_3_2 assign r3_2_3_2$D_IN = r3_0_0_0$D_IN ; assign r3_2_3_2$EN = WILL_FIRE_RL_write && k == 8'd2 && j == 8'd3 && i == 8'd2 ; // register r3_2_3_3 assign r3_2_3_3$D_IN = r3_0_0_0$D_IN ; assign r3_2_3_3$EN = WILL_FIRE_RL_write && k == 8'd3 && j == 8'd3 && i == 8'd2 ; // register r3_3_0_0 assign r3_3_0_0$D_IN = r3_0_0_0$D_IN ; assign r3_3_0_0$EN = WILL_FIRE_RL_write && k == 8'd0 && j == 8'd0 && i == 8'd3 ; // register r3_3_0_1 assign r3_3_0_1$D_IN = r3_0_0_0$D_IN ; assign r3_3_0_1$EN = WILL_FIRE_RL_write && k == 8'd1 && j == 8'd0 && i == 8'd3 ; // register r3_3_0_2 assign r3_3_0_2$D_IN = r3_0_0_0$D_IN ; assign r3_3_0_2$EN = WILL_FIRE_RL_write && k == 8'd2 && j == 8'd0 && i == 8'd3 ; // register r3_3_0_3 assign r3_3_0_3$D_IN = r3_0_0_0$D_IN ; assign r3_3_0_3$EN = WILL_FIRE_RL_write && k == 8'd3 && j == 8'd0 && i == 8'd3 ; // register r3_3_1_0 assign r3_3_1_0$D_IN = r3_0_0_0$D_IN ; assign r3_3_1_0$EN = WILL_FIRE_RL_write && k == 8'd0 && j == 8'd1 && i == 8'd3 ; // register r3_3_1_1 assign r3_3_1_1$D_IN = r3_0_0_0$D_IN ; assign r3_3_1_1$EN = WILL_FIRE_RL_write && k == 8'd1 && j == 8'd1 && i == 8'd3 ; // register r3_3_1_2 assign r3_3_1_2$D_IN = r3_0_0_0$D_IN ; assign r3_3_1_2$EN = WILL_FIRE_RL_write && k == 8'd2 && j == 8'd1 && i == 8'd3 ; // register r3_3_1_3 assign r3_3_1_3$D_IN = r3_0_0_0$D_IN ; assign r3_3_1_3$EN = WILL_FIRE_RL_write && k == 8'd3 && j == 8'd1 && i == 8'd3 ; // register r3_3_2_0 assign r3_3_2_0$D_IN = r3_0_0_0$D_IN ; assign r3_3_2_0$EN = WILL_FIRE_RL_write && k == 8'd0 && j == 8'd2 && i == 8'd3 ; // register r3_3_2_1 assign r3_3_2_1$D_IN = r3_0_0_0$D_IN ; assign r3_3_2_1$EN = WILL_FIRE_RL_write && k == 8'd1 && j == 8'd2 && i == 8'd3 ; // register r3_3_2_2 assign r3_3_2_2$D_IN = r3_0_0_0$D_IN ; assign r3_3_2_2$EN = WILL_FIRE_RL_write && k == 8'd2 && j == 8'd2 && i == 8'd3 ; // register r3_3_2_3 assign r3_3_2_3$D_IN = r3_0_0_0$D_IN ; assign r3_3_2_3$EN = WILL_FIRE_RL_write && k == 8'd3 && j == 8'd2 && i == 8'd3 ; // register r3_3_3_0 assign r3_3_3_0$D_IN = r3_0_0_0$D_IN ; assign r3_3_3_0$EN = WILL_FIRE_RL_write && k == 8'd0 && j == 8'd3 && i == 8'd3 ; // register r3_3_3_1 assign r3_3_3_1$D_IN = r3_0_0_0$D_IN ; assign r3_3_3_1$EN = WILL_FIRE_RL_write && k == 8'd1 && j == 8'd3 && i == 8'd3 ; // register r3_3_3_2 assign r3_3_3_2$D_IN = r3_0_0_0$D_IN ; assign r3_3_3_2$EN = WILL_FIRE_RL_write && k == 8'd2 && j == 8'd3 && i == 8'd3 ; // register r3_3_3_3 assign r3_3_3_3$D_IN = r3_0_0_0$D_IN ; assign r3_3_3_3$EN = WILL_FIRE_RL_write && k == 8'd3 && j == 8'd3 && i == 8'd3 ; // remaining internal signals assign j_53_MUL_k___d202 = j * k ; always@(k or r3_0_0_0 or r3_0_0_1 or r3_0_0_2 or r3_0_0_3) begin case (k) 8'd0: SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_0_2_0_r3_0_0_3__ETC___d145 = r3_0_0_0; 8'd1: SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_0_2_0_r3_0_0_3__ETC___d145 = r3_0_0_1; 8'd2: SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_0_2_0_r3_0_0_3__ETC___d145 = r3_0_0_2; 8'd3: SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_0_2_0_r3_0_0_3__ETC___d145 = r3_0_0_3; default: SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_0_2_0_r3_0_0_3__ETC___d145 = 8'b10101010 /* unspecified value */ ; endcase end always@(k or r3_0_1_0 or r3_0_1_1 or r3_0_1_2 or r3_0_1_3) begin case (k) 8'd0: SEL_ARR_r3_0_1_0_5_r3_0_1_1_7_r3_0_1_2_9_r3_0__ETC___d147 = r3_0_1_0; 8'd1: SEL_ARR_r3_0_1_0_5_r3_0_1_1_7_r3_0_1_2_9_r3_0__ETC___d147 = r3_0_1_1; 8'd2: SEL_ARR_r3_0_1_0_5_r3_0_1_1_7_r3_0_1_2_9_r3_0__ETC___d147 = r3_0_1_2; 8'd3: SEL_ARR_r3_0_1_0_5_r3_0_1_1_7_r3_0_1_2_9_r3_0__ETC___d147 = r3_0_1_3; default: SEL_ARR_r3_0_1_0_5_r3_0_1_1_7_r3_0_1_2_9_r3_0__ETC___d147 = 8'b10101010 /* unspecified value */ ; endcase end always@(k or r3_0_2_0 or r3_0_2_1 or r3_0_2_2 or r3_0_2_3) begin case (k) 8'd0: SEL_ARR_r3_0_2_0_3_r3_0_2_1_5_r3_0_2_2_7_r3_0__ETC___d149 = r3_0_2_0; 8'd1: SEL_ARR_r3_0_2_0_3_r3_0_2_1_5_r3_0_2_2_7_r3_0__ETC___d149 = r3_0_2_1; 8'd2: SEL_ARR_r3_0_2_0_3_r3_0_2_1_5_r3_0_2_2_7_r3_0__ETC___d149 = r3_0_2_2; 8'd3: SEL_ARR_r3_0_2_0_3_r3_0_2_1_5_r3_0_2_2_7_r3_0__ETC___d149 = r3_0_2_3; default: SEL_ARR_r3_0_2_0_3_r3_0_2_1_5_r3_0_2_2_7_r3_0__ETC___d149 = 8'b10101010 /* unspecified value */ ; endcase end always@(k or r3_0_3_0 or r3_0_3_1 or r3_0_3_2 or r3_0_3_3) begin case (k) 8'd0: SEL_ARR_r3_0_3_0_3_r3_0_3_1_5_r3_0_3_2_7_r3_0__ETC___d151 = r3_0_3_0; 8'd1: SEL_ARR_r3_0_3_0_3_r3_0_3_1_5_r3_0_3_2_7_r3_0__ETC___d151 = r3_0_3_1; 8'd2: SEL_ARR_r3_0_3_0_3_r3_0_3_1_5_r3_0_3_2_7_r3_0__ETC___d151 = r3_0_3_2; 8'd3: SEL_ARR_r3_0_3_0_3_r3_0_3_1_5_r3_0_3_2_7_r3_0__ETC___d151 = r3_0_3_3; default: SEL_ARR_r3_0_3_0_3_r3_0_3_1_5_r3_0_3_2_7_r3_0__ETC___d151 = 8'b10101010 /* unspecified value */ ; endcase end always@(k or r3_1_0_0 or r3_1_0_1 or r3_1_0_2 or r3_1_0_3) begin case (k) 8'd0: SEL_ARR_r3_1_0_0_2_r3_1_0_1_4_r3_1_0_2_6_r3_1__ETC___d156 = r3_1_0_0; 8'd1: SEL_ARR_r3_1_0_0_2_r3_1_0_1_4_r3_1_0_2_6_r3_1__ETC___d156 = r3_1_0_1; 8'd2: SEL_ARR_r3_1_0_0_2_r3_1_0_1_4_r3_1_0_2_6_r3_1__ETC___d156 = r3_1_0_2; 8'd3: SEL_ARR_r3_1_0_0_2_r3_1_0_1_4_r3_1_0_2_6_r3_1__ETC___d156 = r3_1_0_3; default: SEL_ARR_r3_1_0_0_2_r3_1_0_1_4_r3_1_0_2_6_r3_1__ETC___d156 = 8'b10101010 /* unspecified value */ ; endcase end always@(k or r3_1_1_0 or r3_1_1_1 or r3_1_1_2 or r3_1_1_3) begin case (k) 8'd0: SEL_ARR_r3_1_1_0_0_r3_1_1_1_2_r3_1_1_2_4_r3_1__ETC___d158 = r3_1_1_0; 8'd1: SEL_ARR_r3_1_1_0_0_r3_1_1_1_2_r3_1_1_2_4_r3_1__ETC___d158 = r3_1_1_1; 8'd2: SEL_ARR_r3_1_1_0_0_r3_1_1_1_2_r3_1_1_2_4_r3_1__ETC___d158 = r3_1_1_2; 8'd3: SEL_ARR_r3_1_1_0_0_r3_1_1_1_2_r3_1_1_2_4_r3_1__ETC___d158 = r3_1_1_3; default: SEL_ARR_r3_1_1_0_0_r3_1_1_1_2_r3_1_1_2_4_r3_1__ETC___d158 = 8'b10101010 /* unspecified value */ ; endcase end always@(k or r3_1_2_0 or r3_1_2_1 or r3_1_2_2 or r3_1_2_3) begin case (k) 8'd0: SEL_ARR_r3_1_2_0_8_r3_1_2_1_0_r3_1_2_2_2_r3_1__ETC___d160 = r3_1_2_0; 8'd1: SEL_ARR_r3_1_2_0_8_r3_1_2_1_0_r3_1_2_2_2_r3_1__ETC___d160 = r3_1_2_1; 8'd2: SEL_ARR_r3_1_2_0_8_r3_1_2_1_0_r3_1_2_2_2_r3_1__ETC___d160 = r3_1_2_2; 8'd3: SEL_ARR_r3_1_2_0_8_r3_1_2_1_0_r3_1_2_2_2_r3_1__ETC___d160 = r3_1_2_3; default: SEL_ARR_r3_1_2_0_8_r3_1_2_1_0_r3_1_2_2_2_r3_1__ETC___d160 = 8'b10101010 /* unspecified value */ ; endcase end always@(k or r3_1_3_0 or r3_1_3_1 or r3_1_3_2 or r3_1_3_3) begin case (k) 8'd0: SEL_ARR_r3_1_3_0_8_r3_1_3_1_0_r3_1_3_2_2_r3_1__ETC___d162 = r3_1_3_0; 8'd1: SEL_ARR_r3_1_3_0_8_r3_1_3_1_0_r3_1_3_2_2_r3_1__ETC___d162 = r3_1_3_1; 8'd2: SEL_ARR_r3_1_3_0_8_r3_1_3_1_0_r3_1_3_2_2_r3_1__ETC___d162 = r3_1_3_2; 8'd3: SEL_ARR_r3_1_3_0_8_r3_1_3_1_0_r3_1_3_2_2_r3_1__ETC___d162 = r3_1_3_3; default: SEL_ARR_r3_1_3_0_8_r3_1_3_1_0_r3_1_3_2_2_r3_1__ETC___d162 = 8'b10101010 /* unspecified value */ ; endcase end always@(k or r3_2_0_0 or r3_2_0_1 or r3_2_0_2 or r3_2_0_3) begin case (k) 8'd0: SEL_ARR_r3_2_0_0_7_r3_2_0_1_9_r3_2_0_2_1_r3_2__ETC___d166 = r3_2_0_0; 8'd1: SEL_ARR_r3_2_0_0_7_r3_2_0_1_9_r3_2_0_2_1_r3_2__ETC___d166 = r3_2_0_1; 8'd2: SEL_ARR_r3_2_0_0_7_r3_2_0_1_9_r3_2_0_2_1_r3_2__ETC___d166 = r3_2_0_2; 8'd3: SEL_ARR_r3_2_0_0_7_r3_2_0_1_9_r3_2_0_2_1_r3_2__ETC___d166 = r3_2_0_3; default: SEL_ARR_r3_2_0_0_7_r3_2_0_1_9_r3_2_0_2_1_r3_2__ETC___d166 = 8'b10101010 /* unspecified value */ ; endcase end always@(k or r3_2_1_0 or r3_2_1_1 or r3_2_1_2 or r3_2_1_3) begin case (k) 8'd0: SEL_ARR_r3_2_1_0_5_r3_2_1_1_7_r3_2_1_2_9_r3_2__ETC___d168 = r3_2_1_0; 8'd1: SEL_ARR_r3_2_1_0_5_r3_2_1_1_7_r3_2_1_2_9_r3_2__ETC___d168 = r3_2_1_1; 8'd2: SEL_ARR_r3_2_1_0_5_r3_2_1_1_7_r3_2_1_2_9_r3_2__ETC___d168 = r3_2_1_2; 8'd3: SEL_ARR_r3_2_1_0_5_r3_2_1_1_7_r3_2_1_2_9_r3_2__ETC___d168 = r3_2_1_3; default: SEL_ARR_r3_2_1_0_5_r3_2_1_1_7_r3_2_1_2_9_r3_2__ETC___d168 = 8'b10101010 /* unspecified value */ ; endcase end always@(k or r3_2_2_0 or r3_2_2_1 or r3_2_2_2 or r3_2_2_3) begin case (k) 8'd0: SEL_ARR_r3_2_2_0_3_r3_2_2_1_5_r3_2_2_2_7_r3_2__ETC___d170 = r3_2_2_0; 8'd1: SEL_ARR_r3_2_2_0_3_r3_2_2_1_5_r3_2_2_2_7_r3_2__ETC___d170 = r3_2_2_1; 8'd2: SEL_ARR_r3_2_2_0_3_r3_2_2_1_5_r3_2_2_2_7_r3_2__ETC___d170 = r3_2_2_2; 8'd3: SEL_ARR_r3_2_2_0_3_r3_2_2_1_5_r3_2_2_2_7_r3_2__ETC___d170 = r3_2_2_3; default: SEL_ARR_r3_2_2_0_3_r3_2_2_1_5_r3_2_2_2_7_r3_2__ETC___d170 = 8'b10101010 /* unspecified value */ ; endcase end always@(k or r3_3_0_0 or r3_3_0_1 or r3_3_0_2 or r3_3_0_3) begin case (k) 8'd0: SEL_ARR_r3_3_0_0_11_r3_3_0_1_13_r3_3_0_2_15_r3_ETC___d176 = r3_3_0_0; 8'd1: SEL_ARR_r3_3_0_0_11_r3_3_0_1_13_r3_3_0_2_15_r3_ETC___d176 = r3_3_0_1; 8'd2: SEL_ARR_r3_3_0_0_11_r3_3_0_1_13_r3_3_0_2_15_r3_ETC___d176 = r3_3_0_2; 8'd3: SEL_ARR_r3_3_0_0_11_r3_3_0_1_13_r3_3_0_2_15_r3_ETC___d176 = r3_3_0_3; default: SEL_ARR_r3_3_0_0_11_r3_3_0_1_13_r3_3_0_2_15_r3_ETC___d176 = 8'b10101010 /* unspecified value */ ; endcase end always@(k or r3_2_3_0 or r3_2_3_1 or r3_2_3_2 or r3_2_3_3) begin case (k) 8'd0: SEL_ARR_r3_2_3_0_02_r3_2_3_1_04_r3_2_3_2_06_r3_ETC___d172 = r3_2_3_0; 8'd1: SEL_ARR_r3_2_3_0_02_r3_2_3_1_04_r3_2_3_2_06_r3_ETC___d172 = r3_2_3_1; 8'd2: SEL_ARR_r3_2_3_0_02_r3_2_3_1_04_r3_2_3_2_06_r3_ETC___d172 = r3_2_3_2; 8'd3: SEL_ARR_r3_2_3_0_02_r3_2_3_1_04_r3_2_3_2_06_r3_ETC___d172 = r3_2_3_3; default: SEL_ARR_r3_2_3_0_02_r3_2_3_1_04_r3_2_3_2_06_r3_ETC___d172 = 8'b10101010 /* unspecified value */ ; endcase end always@(k or r3_3_1_0 or r3_3_1_1 or r3_3_1_2 or r3_3_1_3) begin case (k) 8'd0: SEL_ARR_r3_3_1_0_19_r3_3_1_1_21_r3_3_1_2_23_r3_ETC___d178 = r3_3_1_0; 8'd1: SEL_ARR_r3_3_1_0_19_r3_3_1_1_21_r3_3_1_2_23_r3_ETC___d178 = r3_3_1_1; 8'd2: SEL_ARR_r3_3_1_0_19_r3_3_1_1_21_r3_3_1_2_23_r3_ETC___d178 = r3_3_1_2; 8'd3: SEL_ARR_r3_3_1_0_19_r3_3_1_1_21_r3_3_1_2_23_r3_ETC___d178 = r3_3_1_3; default: SEL_ARR_r3_3_1_0_19_r3_3_1_1_21_r3_3_1_2_23_r3_ETC___d178 = 8'b10101010 /* unspecified value */ ; endcase end always@(k or r3_3_2_0 or r3_3_2_1 or r3_3_2_2 or r3_3_2_3) begin case (k) 8'd0: SEL_ARR_r3_3_2_0_27_r3_3_2_1_29_r3_3_2_2_31_r3_ETC___d180 = r3_3_2_0; 8'd1: SEL_ARR_r3_3_2_0_27_r3_3_2_1_29_r3_3_2_2_31_r3_ETC___d180 = r3_3_2_1; 8'd2: SEL_ARR_r3_3_2_0_27_r3_3_2_1_29_r3_3_2_2_31_r3_ETC___d180 = r3_3_2_2; 8'd3: SEL_ARR_r3_3_2_0_27_r3_3_2_1_29_r3_3_2_2_31_r3_ETC___d180 = r3_3_2_3; default: SEL_ARR_r3_3_2_0_27_r3_3_2_1_29_r3_3_2_2_31_r3_ETC___d180 = 8'b10101010 /* unspecified value */ ; endcase end always@(k or r3_3_3_0 or r3_3_3_1 or r3_3_3_2 or r3_3_3_3) begin case (k) 8'd0: SEL_ARR_r3_3_3_0_35_r3_3_3_1_37_r3_3_3_2_39_r3_ETC___d182 = r3_3_3_0; 8'd1: SEL_ARR_r3_3_3_0_35_r3_3_3_1_37_r3_3_3_2_39_r3_ETC___d182 = r3_3_3_1; 8'd2: SEL_ARR_r3_3_3_0_35_r3_3_3_1_37_r3_3_3_2_39_r3_ETC___d182 = r3_3_3_2; 8'd3: SEL_ARR_r3_3_3_0_35_r3_3_3_1_37_r3_3_3_2_39_r3_ETC___d182 = r3_3_3_3; default: SEL_ARR_r3_3_3_0_35_r3_3_3_1_37_r3_3_3_2_39_r3_ETC___d182 = 8'b10101010 /* unspecified value */ ; endcase end always@(j or SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_0_2_0_r3_0_0_3__ETC___d145 or SEL_ARR_r3_0_1_0_5_r3_0_1_1_7_r3_0_1_2_9_r3_0__ETC___d147 or SEL_ARR_r3_0_2_0_3_r3_0_2_1_5_r3_0_2_2_7_r3_0__ETC___d149 or SEL_ARR_r3_0_3_0_3_r3_0_3_1_5_r3_0_3_2_7_r3_0__ETC___d151) begin case (j) 8'd0: SEL_ARR_SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_0_2_0_r_ETC___d154 = SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_0_2_0_r3_0_0_3__ETC___d145; 8'd1: SEL_ARR_SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_0_2_0_r_ETC___d154 = SEL_ARR_r3_0_1_0_5_r3_0_1_1_7_r3_0_1_2_9_r3_0__ETC___d147; 8'd2: SEL_ARR_SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_0_2_0_r_ETC___d154 = SEL_ARR_r3_0_2_0_3_r3_0_2_1_5_r3_0_2_2_7_r3_0__ETC___d149; 8'd3: SEL_ARR_SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_0_2_0_r_ETC___d154 = SEL_ARR_r3_0_3_0_3_r3_0_3_1_5_r3_0_3_2_7_r3_0__ETC___d151; default: SEL_ARR_SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_0_2_0_r_ETC___d154 = 8'b10101010 /* unspecified value */ ; endcase end always@(j or SEL_ARR_r3_1_0_0_2_r3_1_0_1_4_r3_1_0_2_6_r3_1__ETC___d156 or SEL_ARR_r3_1_1_0_0_r3_1_1_1_2_r3_1_1_2_4_r3_1__ETC___d158 or SEL_ARR_r3_1_2_0_8_r3_1_2_1_0_r3_1_2_2_2_r3_1__ETC___d160 or SEL_ARR_r3_1_3_0_8_r3_1_3_1_0_r3_1_3_2_2_r3_1__ETC___d162) begin case (j) 8'd0: SEL_ARR_SEL_ARR_r3_1_0_0_2_r3_1_0_1_4_r3_1_0_2_ETC___d164 = SEL_ARR_r3_1_0_0_2_r3_1_0_1_4_r3_1_0_2_6_r3_1__ETC___d156; 8'd1: SEL_ARR_SEL_ARR_r3_1_0_0_2_r3_1_0_1_4_r3_1_0_2_ETC___d164 = SEL_ARR_r3_1_1_0_0_r3_1_1_1_2_r3_1_1_2_4_r3_1__ETC___d158; 8'd2: SEL_ARR_SEL_ARR_r3_1_0_0_2_r3_1_0_1_4_r3_1_0_2_ETC___d164 = SEL_ARR_r3_1_2_0_8_r3_1_2_1_0_r3_1_2_2_2_r3_1__ETC___d160; 8'd3: SEL_ARR_SEL_ARR_r3_1_0_0_2_r3_1_0_1_4_r3_1_0_2_ETC___d164 = SEL_ARR_r3_1_3_0_8_r3_1_3_1_0_r3_1_3_2_2_r3_1__ETC___d162; default: SEL_ARR_SEL_ARR_r3_1_0_0_2_r3_1_0_1_4_r3_1_0_2_ETC___d164 = 8'b10101010 /* unspecified value */ ; endcase end always@(j or SEL_ARR_r3_2_0_0_7_r3_2_0_1_9_r3_2_0_2_1_r3_2__ETC___d166 or SEL_ARR_r3_2_1_0_5_r3_2_1_1_7_r3_2_1_2_9_r3_2__ETC___d168 or SEL_ARR_r3_2_2_0_3_r3_2_2_1_5_r3_2_2_2_7_r3_2__ETC___d170 or SEL_ARR_r3_2_3_0_02_r3_2_3_1_04_r3_2_3_2_06_r3_ETC___d172) begin case (j) 8'd0: SEL_ARR_SEL_ARR_r3_2_0_0_7_r3_2_0_1_9_r3_2_0_2_ETC___d174 = SEL_ARR_r3_2_0_0_7_r3_2_0_1_9_r3_2_0_2_1_r3_2__ETC___d166; 8'd1: SEL_ARR_SEL_ARR_r3_2_0_0_7_r3_2_0_1_9_r3_2_0_2_ETC___d174 = SEL_ARR_r3_2_1_0_5_r3_2_1_1_7_r3_2_1_2_9_r3_2__ETC___d168; 8'd2: SEL_ARR_SEL_ARR_r3_2_0_0_7_r3_2_0_1_9_r3_2_0_2_ETC___d174 = SEL_ARR_r3_2_2_0_3_r3_2_2_1_5_r3_2_2_2_7_r3_2__ETC___d170; 8'd3: SEL_ARR_SEL_ARR_r3_2_0_0_7_r3_2_0_1_9_r3_2_0_2_ETC___d174 = SEL_ARR_r3_2_3_0_02_r3_2_3_1_04_r3_2_3_2_06_r3_ETC___d172; default: SEL_ARR_SEL_ARR_r3_2_0_0_7_r3_2_0_1_9_r3_2_0_2_ETC___d174 = 8'b10101010 /* unspecified value */ ; endcase end always@(j or SEL_ARR_r3_3_0_0_11_r3_3_0_1_13_r3_3_0_2_15_r3_ETC___d176 or SEL_ARR_r3_3_1_0_19_r3_3_1_1_21_r3_3_1_2_23_r3_ETC___d178 or SEL_ARR_r3_3_2_0_27_r3_3_2_1_29_r3_3_2_2_31_r3_ETC___d180 or SEL_ARR_r3_3_3_0_35_r3_3_3_1_37_r3_3_3_2_39_r3_ETC___d182) begin case (j) 8'd0: SEL_ARR_SEL_ARR_r3_3_0_0_11_r3_3_0_1_13_r3_3_0_ETC___d184 = SEL_ARR_r3_3_0_0_11_r3_3_0_1_13_r3_3_0_2_15_r3_ETC___d176; 8'd1: SEL_ARR_SEL_ARR_r3_3_0_0_11_r3_3_0_1_13_r3_3_0_ETC___d184 = SEL_ARR_r3_3_1_0_19_r3_3_1_1_21_r3_3_1_2_23_r3_ETC___d178; 8'd2: SEL_ARR_SEL_ARR_r3_3_0_0_11_r3_3_0_1_13_r3_3_0_ETC___d184 = SEL_ARR_r3_3_2_0_27_r3_3_2_1_29_r3_3_2_2_31_r3_ETC___d180; 8'd3: SEL_ARR_SEL_ARR_r3_3_0_0_11_r3_3_0_1_13_r3_3_0_ETC___d184 = SEL_ARR_r3_3_3_0_35_r3_3_3_1_37_r3_3_3_2_39_r3_ETC___d182; default: SEL_ARR_SEL_ARR_r3_3_0_0_11_r3_3_0_1_13_r3_3_0_ETC___d184 = 8'b10101010 /* unspecified value */ ; endcase end always@(i or SEL_ARR_SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_0_2_0_r_ETC___d154 or SEL_ARR_SEL_ARR_r3_1_0_0_2_r3_1_0_1_4_r3_1_0_2_ETC___d164 or SEL_ARR_SEL_ARR_r3_2_0_0_7_r3_2_0_1_9_r3_2_0_2_ETC___d174 or SEL_ARR_SEL_ARR_r3_3_0_0_11_r3_3_0_1_13_r3_3_0_ETC___d184) begin case (i) 8'd0: SEL_ARR_SEL_ARR_SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_ETC___d187 = SEL_ARR_SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_0_2_0_r_ETC___d154; 8'd1: SEL_ARR_SEL_ARR_SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_ETC___d187 = SEL_ARR_SEL_ARR_r3_1_0_0_2_r3_1_0_1_4_r3_1_0_2_ETC___d164; 8'd2: SEL_ARR_SEL_ARR_SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_ETC___d187 = SEL_ARR_SEL_ARR_r3_2_0_0_7_r3_2_0_1_9_r3_2_0_2_ETC___d174; 8'd3: SEL_ARR_SEL_ARR_SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_ETC___d187 = SEL_ARR_SEL_ARR_r3_3_0_0_11_r3_3_0_1_13_r3_3_0_ETC___d184; default: SEL_ARR_SEL_ARR_SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_ETC___d187 = 8'b10101010 /* unspecified value */ ; endcase end // handling of inlined registers always@(posedge CLK) begin if (RST_N == `BSV_RESET_VALUE) begin i <= `BSV_ASSIGNMENT_DELAY 8'd0; j <= `BSV_ASSIGNMENT_DELAY 8'd0; k <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_0_0_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_0_0_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_0_0_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_0_0_3 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_0_1_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_0_1_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_0_1_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_0_1_3 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_0_2_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_0_2_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_0_2_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_0_2_3 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_0_3_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_0_3_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_0_3_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_0_3_3 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_1_0_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_1_0_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_1_0_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_1_0_3 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_1_1_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_1_1_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_1_1_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_1_1_3 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_1_2_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_1_2_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_1_2_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_1_2_3 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_1_3_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_1_3_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_1_3_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_1_3_3 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_2_0_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_2_0_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_2_0_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_2_0_3 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_2_1_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_2_1_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_2_1_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_2_1_3 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_2_2_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_2_2_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_2_2_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_2_2_3 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_2_3_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_2_3_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_2_3_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_2_3_3 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_3_0_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_3_0_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_3_0_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_3_0_3 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_3_1_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_3_1_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_3_1_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_3_1_3 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_3_2_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_3_2_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_3_2_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_3_2_3 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_3_3_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_3_3_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_3_3_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; r3_3_3_3 <= `BSV_ASSIGNMENT_DELAY 8'd0; end else begin if (i$EN) i <= `BSV_ASSIGNMENT_DELAY i$D_IN; if (j$EN) j <= `BSV_ASSIGNMENT_DELAY j$D_IN; if (k$EN) k <= `BSV_ASSIGNMENT_DELAY k$D_IN; if (r3_0_0_0$EN) r3_0_0_0 <= `BSV_ASSIGNMENT_DELAY r3_0_0_0$D_IN; if (r3_0_0_1$EN) r3_0_0_1 <= `BSV_ASSIGNMENT_DELAY r3_0_0_1$D_IN; if (r3_0_0_2$EN) r3_0_0_2 <= `BSV_ASSIGNMENT_DELAY r3_0_0_2$D_IN; if (r3_0_0_3$EN) r3_0_0_3 <= `BSV_ASSIGNMENT_DELAY r3_0_0_3$D_IN; if (r3_0_1_0$EN) r3_0_1_0 <= `BSV_ASSIGNMENT_DELAY r3_0_1_0$D_IN; if (r3_0_1_1$EN) r3_0_1_1 <= `BSV_ASSIGNMENT_DELAY r3_0_1_1$D_IN; if (r3_0_1_2$EN) r3_0_1_2 <= `BSV_ASSIGNMENT_DELAY r3_0_1_2$D_IN; if (r3_0_1_3$EN) r3_0_1_3 <= `BSV_ASSIGNMENT_DELAY r3_0_1_3$D_IN; if (r3_0_2_0$EN) r3_0_2_0 <= `BSV_ASSIGNMENT_DELAY r3_0_2_0$D_IN; if (r3_0_2_1$EN) r3_0_2_1 <= `BSV_ASSIGNMENT_DELAY r3_0_2_1$D_IN; if (r3_0_2_2$EN) r3_0_2_2 <= `BSV_ASSIGNMENT_DELAY r3_0_2_2$D_IN; if (r3_0_2_3$EN) r3_0_2_3 <= `BSV_ASSIGNMENT_DELAY r3_0_2_3$D_IN; if (r3_0_3_0$EN) r3_0_3_0 <= `BSV_ASSIGNMENT_DELAY r3_0_3_0$D_IN; if (r3_0_3_1$EN) r3_0_3_1 <= `BSV_ASSIGNMENT_DELAY r3_0_3_1$D_IN; if (r3_0_3_2$EN) r3_0_3_2 <= `BSV_ASSIGNMENT_DELAY r3_0_3_2$D_IN; if (r3_0_3_3$EN) r3_0_3_3 <= `BSV_ASSIGNMENT_DELAY r3_0_3_3$D_IN; if (r3_1_0_0$EN) r3_1_0_0 <= `BSV_ASSIGNMENT_DELAY r3_1_0_0$D_IN; if (r3_1_0_1$EN) r3_1_0_1 <= `BSV_ASSIGNMENT_DELAY r3_1_0_1$D_IN; if (r3_1_0_2$EN) r3_1_0_2 <= `BSV_ASSIGNMENT_DELAY r3_1_0_2$D_IN; if (r3_1_0_3$EN) r3_1_0_3 <= `BSV_ASSIGNMENT_DELAY r3_1_0_3$D_IN; if (r3_1_1_0$EN) r3_1_1_0 <= `BSV_ASSIGNMENT_DELAY r3_1_1_0$D_IN; if (r3_1_1_1$EN) r3_1_1_1 <= `BSV_ASSIGNMENT_DELAY r3_1_1_1$D_IN; if (r3_1_1_2$EN) r3_1_1_2 <= `BSV_ASSIGNMENT_DELAY r3_1_1_2$D_IN; if (r3_1_1_3$EN) r3_1_1_3 <= `BSV_ASSIGNMENT_DELAY r3_1_1_3$D_IN; if (r3_1_2_0$EN) r3_1_2_0 <= `BSV_ASSIGNMENT_DELAY r3_1_2_0$D_IN; if (r3_1_2_1$EN) r3_1_2_1 <= `BSV_ASSIGNMENT_DELAY r3_1_2_1$D_IN; if (r3_1_2_2$EN) r3_1_2_2 <= `BSV_ASSIGNMENT_DELAY r3_1_2_2$D_IN; if (r3_1_2_3$EN) r3_1_2_3 <= `BSV_ASSIGNMENT_DELAY r3_1_2_3$D_IN; if (r3_1_3_0$EN) r3_1_3_0 <= `BSV_ASSIGNMENT_DELAY r3_1_3_0$D_IN; if (r3_1_3_1$EN) r3_1_3_1 <= `BSV_ASSIGNMENT_DELAY r3_1_3_1$D_IN; if (r3_1_3_2$EN) r3_1_3_2 <= `BSV_ASSIGNMENT_DELAY r3_1_3_2$D_IN; if (r3_1_3_3$EN) r3_1_3_3 <= `BSV_ASSIGNMENT_DELAY r3_1_3_3$D_IN; if (r3_2_0_0$EN) r3_2_0_0 <= `BSV_ASSIGNMENT_DELAY r3_2_0_0$D_IN; if (r3_2_0_1$EN) r3_2_0_1 <= `BSV_ASSIGNMENT_DELAY r3_2_0_1$D_IN; if (r3_2_0_2$EN) r3_2_0_2 <= `BSV_ASSIGNMENT_DELAY r3_2_0_2$D_IN; if (r3_2_0_3$EN) r3_2_0_3 <= `BSV_ASSIGNMENT_DELAY r3_2_0_3$D_IN; if (r3_2_1_0$EN) r3_2_1_0 <= `BSV_ASSIGNMENT_DELAY r3_2_1_0$D_IN; if (r3_2_1_1$EN) r3_2_1_1 <= `BSV_ASSIGNMENT_DELAY r3_2_1_1$D_IN; if (r3_2_1_2$EN) r3_2_1_2 <= `BSV_ASSIGNMENT_DELAY r3_2_1_2$D_IN; if (r3_2_1_3$EN) r3_2_1_3 <= `BSV_ASSIGNMENT_DELAY r3_2_1_3$D_IN; if (r3_2_2_0$EN) r3_2_2_0 <= `BSV_ASSIGNMENT_DELAY r3_2_2_0$D_IN; if (r3_2_2_1$EN) r3_2_2_1 <= `BSV_ASSIGNMENT_DELAY r3_2_2_1$D_IN; if (r3_2_2_2$EN) r3_2_2_2 <= `BSV_ASSIGNMENT_DELAY r3_2_2_2$D_IN; if (r3_2_2_3$EN) r3_2_2_3 <= `BSV_ASSIGNMENT_DELAY r3_2_2_3$D_IN; if (r3_2_3_0$EN) r3_2_3_0 <= `BSV_ASSIGNMENT_DELAY r3_2_3_0$D_IN; if (r3_2_3_1$EN) r3_2_3_1 <= `BSV_ASSIGNMENT_DELAY r3_2_3_1$D_IN; if (r3_2_3_2$EN) r3_2_3_2 <= `BSV_ASSIGNMENT_DELAY r3_2_3_2$D_IN; if (r3_2_3_3$EN) r3_2_3_3 <= `BSV_ASSIGNMENT_DELAY r3_2_3_3$D_IN; if (r3_3_0_0$EN) r3_3_0_0 <= `BSV_ASSIGNMENT_DELAY r3_3_0_0$D_IN; if (r3_3_0_1$EN) r3_3_0_1 <= `BSV_ASSIGNMENT_DELAY r3_3_0_1$D_IN; if (r3_3_0_2$EN) r3_3_0_2 <= `BSV_ASSIGNMENT_DELAY r3_3_0_2$D_IN; if (r3_3_0_3$EN) r3_3_0_3 <= `BSV_ASSIGNMENT_DELAY r3_3_0_3$D_IN; if (r3_3_1_0$EN) r3_3_1_0 <= `BSV_ASSIGNMENT_DELAY r3_3_1_0$D_IN; if (r3_3_1_1$EN) r3_3_1_1 <= `BSV_ASSIGNMENT_DELAY r3_3_1_1$D_IN; if (r3_3_1_2$EN) r3_3_1_2 <= `BSV_ASSIGNMENT_DELAY r3_3_1_2$D_IN; if (r3_3_1_3$EN) r3_3_1_3 <= `BSV_ASSIGNMENT_DELAY r3_3_1_3$D_IN; if (r3_3_2_0$EN) r3_3_2_0 <= `BSV_ASSIGNMENT_DELAY r3_3_2_0$D_IN; if (r3_3_2_1$EN) r3_3_2_1 <= `BSV_ASSIGNMENT_DELAY r3_3_2_1$D_IN; if (r3_3_2_2$EN) r3_3_2_2 <= `BSV_ASSIGNMENT_DELAY r3_3_2_2$D_IN; if (r3_3_2_3$EN) r3_3_2_3 <= `BSV_ASSIGNMENT_DELAY r3_3_2_3$D_IN; if (r3_3_3_0$EN) r3_3_3_0 <= `BSV_ASSIGNMENT_DELAY r3_3_3_0$D_IN; if (r3_3_3_1$EN) r3_3_3_1 <= `BSV_ASSIGNMENT_DELAY r3_3_3_1$D_IN; if (r3_3_3_2$EN) r3_3_3_2 <= `BSV_ASSIGNMENT_DELAY r3_3_3_2$D_IN; if (r3_3_3_3$EN) r3_3_3_3 <= `BSV_ASSIGNMENT_DELAY r3_3_3_3$D_IN; end end // synopsys translate_off `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS initial begin i = 8'hAA; j = 8'hAA; k = 8'hAA; r3_0_0_0 = 8'hAA; r3_0_0_1 = 8'hAA; r3_0_0_2 = 8'hAA; r3_0_0_3 = 8'hAA; r3_0_1_0 = 8'hAA; r3_0_1_1 = 8'hAA; r3_0_1_2 = 8'hAA; r3_0_1_3 = 8'hAA; r3_0_2_0 = 8'hAA; r3_0_2_1 = 8'hAA; r3_0_2_2 = 8'hAA; r3_0_2_3 = 8'hAA; r3_0_3_0 = 8'hAA; r3_0_3_1 = 8'hAA; r3_0_3_2 = 8'hAA; r3_0_3_3 = 8'hAA; r3_1_0_0 = 8'hAA; r3_1_0_1 = 8'hAA; r3_1_0_2 = 8'hAA; r3_1_0_3 = 8'hAA; r3_1_1_0 = 8'hAA; r3_1_1_1 = 8'hAA; r3_1_1_2 = 8'hAA; r3_1_1_3 = 8'hAA; r3_1_2_0 = 8'hAA; r3_1_2_1 = 8'hAA; r3_1_2_2 = 8'hAA; r3_1_2_3 = 8'hAA; r3_1_3_0 = 8'hAA; r3_1_3_1 = 8'hAA; r3_1_3_2 = 8'hAA; r3_1_3_3 = 8'hAA; r3_2_0_0 = 8'hAA; r3_2_0_1 = 8'hAA; r3_2_0_2 = 8'hAA; r3_2_0_3 = 8'hAA; r3_2_1_0 = 8'hAA; r3_2_1_1 = 8'hAA; r3_2_1_2 = 8'hAA; r3_2_1_3 = 8'hAA; r3_2_2_0 = 8'hAA; r3_2_2_1 = 8'hAA; r3_2_2_2 = 8'hAA; r3_2_2_3 = 8'hAA; r3_2_3_0 = 8'hAA; r3_2_3_1 = 8'hAA; r3_2_3_2 = 8'hAA; r3_2_3_3 = 8'hAA; r3_3_0_0 = 8'hAA; r3_3_0_1 = 8'hAA; r3_3_0_2 = 8'hAA; r3_3_0_3 = 8'hAA; r3_3_1_0 = 8'hAA; r3_3_1_1 = 8'hAA; r3_3_1_2 = 8'hAA; r3_3_1_3 = 8'hAA; r3_3_2_0 = 8'hAA; r3_3_2_1 = 8'hAA; r3_3_2_2 = 8'hAA; r3_3_2_3 = 8'hAA; r3_3_3_0 = 8'hAA; r3_3_3_1 = 8'hAA; r3_3_3_2 = 8'hAA; r3_3_3_3 = 8'hAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on // handling of system tasks // synopsys translate_off always@(negedge CLK) begin #0; if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd0), $signed(32'd0), $signed(32'd0), $unsigned(r3_0_0_0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd0), $signed(32'd0), $signed(32'd1), $unsigned(r3_0_0_1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd0), $signed(32'd0), $signed(32'd2), $unsigned(r3_0_0_2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd0), $signed(32'd0), $signed(32'd3), $unsigned(r3_0_0_3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd0), $signed(32'd1), $signed(32'd0), $unsigned(r3_0_1_0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd0), $signed(32'd1), $signed(32'd1), $unsigned(r3_0_1_1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd0), $signed(32'd1), $signed(32'd2), $unsigned(r3_0_1_2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd0), $signed(32'd1), $signed(32'd3), $unsigned(r3_0_1_3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd0), $signed(32'd2), $signed(32'd0), $unsigned(r3_0_2_0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd0), $signed(32'd2), $signed(32'd1), $unsigned(r3_0_2_1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd0), $signed(32'd2), $signed(32'd2), $unsigned(r3_0_2_2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd4)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd0), $signed(32'd2), $signed(32'd3), $unsigned(r3_0_2_3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd6)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd0), $signed(32'd3), $signed(32'd0), $unsigned(r3_0_3_0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd0), $signed(32'd3), $signed(32'd1), $unsigned(r3_0_3_1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd0), $signed(32'd3), $signed(32'd2), $unsigned(r3_0_3_2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd6)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd0), $signed(32'd3), $signed(32'd3), $unsigned(r3_0_3_3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd9)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd1), $signed(32'd0), $signed(32'd0), $unsigned(r3_1_0_0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd1), $signed(32'd0), $signed(32'd1), $unsigned(r3_1_0_1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd1), $signed(32'd0), $signed(32'd2), $unsigned(r3_1_0_2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd1), $signed(32'd0), $signed(32'd3), $unsigned(r3_1_0_3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd1), $signed(32'd1), $signed(32'd0), $unsigned(r3_1_1_0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd1), $signed(32'd1), $signed(32'd1), $unsigned(r3_1_1_1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd1), $signed(32'd1), $signed(32'd2), $unsigned(r3_1_1_2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd1), $signed(32'd1), $signed(32'd3), $unsigned(r3_1_1_3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd4)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd1), $signed(32'd2), $signed(32'd0), $unsigned(r3_1_2_0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd1), $signed(32'd2), $signed(32'd1), $unsigned(r3_1_2_1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd1), $signed(32'd2), $signed(32'd2), $unsigned(r3_1_2_2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd5)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd1), $signed(32'd2), $signed(32'd3), $unsigned(r3_1_2_3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd7)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd1), $signed(32'd3), $signed(32'd0), $unsigned(r3_1_3_0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd1), $signed(32'd3), $signed(32'd1), $unsigned(r3_1_3_1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd4)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd1), $signed(32'd3), $signed(32'd2), $unsigned(r3_1_3_2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd7)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd1), $signed(32'd3), $signed(32'd3), $unsigned(r3_1_3_3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd2), $signed(32'd0), $signed(32'd0), $unsigned(r3_2_0_0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd2), $signed(32'd0), $signed(32'd1), $unsigned(r3_2_0_1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd2), $signed(32'd0), $signed(32'd2), $unsigned(r3_2_0_2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd2), $signed(32'd0), $signed(32'd3), $unsigned(r3_2_0_3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd2), $signed(32'd1), $signed(32'd0), $unsigned(r3_2_1_0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd2), $signed(32'd1), $signed(32'd1), $unsigned(r3_2_1_1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd2), $signed(32'd1), $signed(32'd2), $unsigned(r3_2_1_2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd4)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd2), $signed(32'd1), $signed(32'd3), $unsigned(r3_2_1_3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd5)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd2), $signed(32'd2), $signed(32'd0), $unsigned(r3_2_2_0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd2), $signed(32'd2), $signed(32'd1), $unsigned(r3_2_2_1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd4)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd2), $signed(32'd2), $signed(32'd2), $unsigned(r3_2_2_2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd6)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd2), $signed(32'd2), $signed(32'd3), $unsigned(r3_2_2_3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd8)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd2), $signed(32'd3), $signed(32'd0), $unsigned(r3_2_3_0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd2), $signed(32'd3), $signed(32'd1), $unsigned(r3_2_3_1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd5)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd2), $signed(32'd3), $signed(32'd2), $unsigned(r3_2_3_2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd8)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd2), $signed(32'd3), $signed(32'd3), $unsigned(r3_2_3_3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd11)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd3), $signed(32'd0), $signed(32'd0), $unsigned(r3_3_0_0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd3), $signed(32'd0), $signed(32'd1), $unsigned(r3_3_0_1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd3), $signed(32'd0), $signed(32'd2), $unsigned(r3_3_0_2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd3), $signed(32'd0), $signed(32'd3), $unsigned(r3_3_0_3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd3), $signed(32'd1), $signed(32'd0), $unsigned(r3_3_1_0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd3), $signed(32'd1), $signed(32'd1), $unsigned(r3_3_1_1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd4)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd3), $signed(32'd1), $signed(32'd2), $unsigned(r3_3_1_2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd5)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd3), $signed(32'd1), $signed(32'd3), $unsigned(r3_3_1_3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd6)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd3), $signed(32'd2), $signed(32'd0), $unsigned(r3_3_2_0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd3), $signed(32'd2), $signed(32'd1), $unsigned(r3_3_2_1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd5)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd3), $signed(32'd2), $signed(32'd2), $unsigned(r3_3_2_2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd7)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd3), $signed(32'd2), $signed(32'd3), $unsigned(r3_3_2_3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd9)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd3), $signed(32'd3), $signed(32'd0), $unsigned(r3_3_3_0)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd3), $signed(32'd3), $signed(32'd1), $unsigned(r3_3_3_1)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd6)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd3), $signed(32'd3), $signed(32'd2), $unsigned(r3_3_3_2)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd9)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("r3[%0d][%0d][%0d] = %0d", $signed(32'd3), $signed(32'd3), $signed(32'd3), $unsigned(r3_3_3_3)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $display("i + (j * k) = %0d", $signed(32'd12)); if (RST_N != `BSV_RESET_VALUE) if (k == 8'd4) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) $display("Current field", $unsigned(SEL_ARR_SEL_ARR_SEL_ARR_r3_0_0_0_r3_0_0_1_r3_0_ETC___d187)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_write) $display("Writing r3[%0d][%0d][%0d]", $unsigned(i), $unsigned(j), $unsigned(k)); end // synopsys translate_on endmodule // sysArrayReg3D