// // Generated by Bluespec Compiler // // // Ports: // Name I/O size props // _read O 5 reg // CLK I 1 clock // RST_N I 1 reset // incr_val I 5 // decr_val I 5 // update_val I 5 // _write_val I 5 // EN_incr I 1 // EN_decr I 1 // EN_update I 1 // EN__write I 1 // // No combinational paths from inputs to outputs // // `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif `ifdef BSV_POSITIVE_RESET `define BSV_RESET_VALUE 1'b1 `define BSV_RESET_EDGE posedge `else `define BSV_RESET_VALUE 1'b0 `define BSV_RESET_EDGE negedge `endif module sysCntrSched(CLK, RST_N, incr_val, EN_incr, decr_val, EN_decr, update_val, EN_update, _write_val, EN__write, _read); input CLK; input RST_N; // action method incr input [4 : 0] incr_val; input EN_incr; // action method decr input [4 : 0] decr_val; input EN_decr; // action method update input [4 : 0] update_val; input EN_update; // action method _write input [4 : 0] _write_val; input EN__write; // value method _read output [4 : 0] _read; // signals for module outputs wire [4 : 0] _read; // ports of submodule cntr wire [4 : 0] cntr$DATA_A, cntr$DATA_B, cntr$DATA_C, cntr$DATA_F, cntr$Q_OUT; wire cntr$ADDA, cntr$ADDB, cntr$SETC, cntr$SETF; // value method _read assign _read = cntr$Q_OUT ; // submodule cntr Counter #(.width(32'd5), .init(5'd0)) cntr(.CLK(CLK), .RST(RST_N), .DATA_A(cntr$DATA_A), .DATA_B(cntr$DATA_B), .DATA_C(cntr$DATA_C), .DATA_F(cntr$DATA_F), .ADDA(cntr$ADDA), .ADDB(cntr$ADDB), .SETC(cntr$SETC), .SETF(cntr$SETF), .Q_OUT(cntr$Q_OUT)); // submodule cntr assign cntr$DATA_A = incr_val ; assign cntr$DATA_B = -decr_val ; assign cntr$DATA_C = update_val ; assign cntr$DATA_F = _write_val ; assign cntr$ADDA = EN_incr ; assign cntr$ADDB = EN_decr ; assign cntr$SETC = EN_update ; assign cntr$SETF = EN__write ; endmodule // sysCntrSched