//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 reset
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkFIFOContextTest(CLK,
			 RST_N);
  input  CLK;
  input  RST_N;

  // ports of submodule t1_q1_q
  wire [31 : 0] t1_q1_q$D_IN;
  wire t1_q1_q$CLR, t1_q1_q$DEQ, t1_q1_q$ENQ;

  // ports of submodule t1_q2_q
  wire [31 : 0] t1_q2_q$D_IN;
  wire t1_q2_q$CLR, t1_q2_q$DEQ, t1_q2_q$ENQ;

  // ports of submodule t1_q3_q
  wire [31 : 0] t1_q3_q$D_IN;
  wire t1_q3_q$CLR, t1_q3_q$DEQ, t1_q3_q$ENQ;

  // ports of submodule t2_q1_q
  wire [31 : 0] t2_q1_q$D_IN;
  wire t2_q1_q$CLR, t2_q1_q$DEQ, t2_q1_q$ENQ;

  // ports of submodule t2_q2_q
  wire [31 : 0] t2_q2_q$D_IN;
  wire t2_q2_q$CLR, t2_q2_q$DEQ, t2_q2_q$ENQ;

  // ports of submodule t2_q3_q
  wire [31 : 0] t2_q3_q$D_IN;
  wire t2_q3_q$CLR, t2_q3_q$DEQ, t2_q3_q$ENQ;

  // submodule t1_q1_q
  FIFO1 #(.width(32'd32), .guarded(1'd1)) t1_q1_q(.RST(RST_N),
						  .CLK(CLK),
						  .D_IN(t1_q1_q$D_IN),
						  .ENQ(t1_q1_q$ENQ),
						  .DEQ(t1_q1_q$DEQ),
						  .CLR(t1_q1_q$CLR),
						  .D_OUT(),
						  .FULL_N(),
						  .EMPTY_N());

  // submodule t1_q2_q
  FIFO2 #(.width(32'd32), .guarded(1'd1)) t1_q2_q(.RST(RST_N),
						  .CLK(CLK),
						  .D_IN(t1_q2_q$D_IN),
						  .ENQ(t1_q2_q$ENQ),
						  .DEQ(t1_q2_q$DEQ),
						  .CLR(t1_q2_q$CLR),
						  .D_OUT(),
						  .FULL_N(),
						  .EMPTY_N());

  // submodule t1_q3_q
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(1'd1)) t1_q3_q(.RST(RST_N),
				      .CLK(CLK),
				      .D_IN(t1_q3_q$D_IN),
				      .ENQ(t1_q3_q$ENQ),
				      .DEQ(t1_q3_q$DEQ),
				      .CLR(t1_q3_q$CLR),
				      .D_OUT(),
				      .FULL_N(),
				      .EMPTY_N());

  // submodule t2_q1_q
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd4),
	      .p3cntr_width(32'd2),
	      .guarded(1'd1)) t2_q1_q(.RST(RST_N),
				      .CLK(CLK),
				      .D_IN(t2_q1_q$D_IN),
				      .ENQ(t2_q1_q$ENQ),
				      .DEQ(t2_q1_q$DEQ),
				      .CLR(t2_q1_q$CLR),
				      .D_OUT(),
				      .FULL_N(),
				      .EMPTY_N());

  // submodule t2_q2_q
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd5),
	      .p3cntr_width(32'd2),
	      .guarded(1'd1)) t2_q2_q(.RST(RST_N),
				      .CLK(CLK),
				      .D_IN(t2_q2_q$D_IN),
				      .ENQ(t2_q2_q$ENQ),
				      .DEQ(t2_q2_q$DEQ),
				      .CLR(t2_q2_q$CLR),
				      .D_OUT(),
				      .FULL_N(),
				      .EMPTY_N());

  // submodule t2_q3_q
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd6),
	      .p3cntr_width(32'd3),
	      .guarded(1'd1)) t2_q3_q(.RST(RST_N),
				      .CLK(CLK),
				      .D_IN(t2_q3_q$D_IN),
				      .ENQ(t2_q3_q$ENQ),
				      .DEQ(t2_q3_q$DEQ),
				      .CLR(t2_q3_q$CLR),
				      .D_OUT(),
				      .FULL_N(),
				      .EMPTY_N());

  // submodule t1_q1_q
  assign t1_q1_q$D_IN = 32'h0 ;
  assign t1_q1_q$ENQ = 1'b0 ;
  assign t1_q1_q$DEQ = 1'b0 ;
  assign t1_q1_q$CLR = 1'b0 ;

  // submodule t1_q2_q
  assign t1_q2_q$D_IN = 32'h0 ;
  assign t1_q2_q$ENQ = 1'b0 ;
  assign t1_q2_q$DEQ = 1'b0 ;
  assign t1_q2_q$CLR = 1'b0 ;

  // submodule t1_q3_q
  assign t1_q3_q$D_IN = 32'h0 ;
  assign t1_q3_q$ENQ = 1'b0 ;
  assign t1_q3_q$DEQ = 1'b0 ;
  assign t1_q3_q$CLR = 1'b0 ;

  // submodule t2_q1_q
  assign t2_q1_q$D_IN = 32'h0 ;
  assign t2_q1_q$ENQ = 1'b0 ;
  assign t2_q1_q$DEQ = 1'b0 ;
  assign t2_q1_q$CLR = 1'b0 ;

  // submodule t2_q2_q
  assign t2_q2_q$D_IN = 32'h0 ;
  assign t2_q2_q$ENQ = 1'b0 ;
  assign t2_q2_q$DEQ = 1'b0 ;
  assign t2_q2_q$CLR = 1'b0 ;

  // submodule t2_q3_q
  assign t2_q3_q$D_IN = 32'h0 ;
  assign t2_q3_q$ENQ = 1'b0 ;
  assign t2_q3_q$DEQ = 1'b0 ;
  assign t2_q3_q$CLR = 1'b0 ;

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    $display("I love the number %0d", $signed(32'd7));
  end
  // synopsys translate_on
endmodule  // mkFIFOContextTest