//
// Generated by Bluespec Compiler
//
//
//
// Method conflict info:
// (none)
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST                          I     1 reset
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif

module mkTestENBypassWire2(CLK,
			   RST);
  input  CLK;
  input  RST;

  // register counter
  reg [31 : 0] counter;
  wire [31 : 0] counter$D_IN;
  wire counter$EN;

  // register toggle
  reg toggle;
  wire toggle$D_IN, toggle$EN;

  // ports of submodule testWire
  wire [31 : 0] testWire$WGET, testWire$WVAL;

  // remaining internal signals
  wire [63 : 0] counter_MUL_counter___d5;

  // submodule testWire
  BypassWire #(.width(32'd32)) testWire(.WVAL(testWire$WVAL),
					.WGET(testWire$WGET));

  // register counter
  assign counter$D_IN = counter + 32'd1 ;
  assign counter$EN = 1'd1 ;

  // register toggle
  assign toggle$D_IN = !toggle ;
  assign toggle$EN = 1'd1 ;

  // submodule testWire
  assign testWire$WVAL = toggle ? counter_MUL_counter___d5[31:0] : 32'd0 ;

  // remaining internal signals
  assign counter_MUL_counter___d5 = counter * counter ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (!RST)
      begin
        counter <= `BSV_ASSIGNMENT_DELAY 32'd0;
	toggle <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (counter$EN) counter <= `BSV_ASSIGNMENT_DELAY counter$D_IN;
	if (toggle$EN) toggle <= `BSV_ASSIGNMENT_DELAY toggle$D_IN;
      end
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    counter = 32'hAAAAAAAA;
    toggle = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST) $display("Wire: %h", testWire$WGET);
  end
  // synopsys translate_on
endmodule  // mkTestENBypassWire2