//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 unused
// RST_N                          I     1 unused
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkDefaultValue1(CLK,
		       RST_N);
  input  CLK;
  input  RST_N;

  // ports of submodule d1
  wire [6 : 0] d1$D_IN;

  // ports of submodule disabled_clock
  wire disabled_clock$CLK_IN,
       disabled_clock$CLK_IN_EN,
       disabled_clock$CLK_OUT,
       disabled_clock$COND_IN,
       disabled_clock$COND_IN_EN;

  // submodule d1
  AlwaysWrite #(.width(32'd7)) d1(.CLK(disabled_clock$CLK_OUT),
				  .CLK_GATE(1'b1),
				  .D_IN(d1$D_IN));

  // submodule disabled_clock
  MakeClock #(.initVal(1'd0), .initGate(1'd1)) disabled_clock(.CLK(1'd0),
							      .RST(!`BSV_RESET_VALUE),
							      .CLK_IN(disabled_clock$CLK_IN),
							      .COND_IN(disabled_clock$COND_IN),
							      .CLK_IN_EN(disabled_clock$CLK_IN_EN),
							      .COND_IN_EN(disabled_clock$COND_IN_EN),
							      .CLK_VAL_OUT(),
							      .COND_OUT(),
							      .CLK_GATE_OUT(),
							      .CLK_OUT(disabled_clock$CLK_OUT));

  // submodule d1
  assign d1$D_IN = 7'd5 ;

  // submodule disabled_clock
  assign disabled_clock$CLK_IN = 1'b0 ;
  assign disabled_clock$COND_IN = 1'b0 ;
  assign disabled_clock$CLK_IN_EN = 1'b0 ;
  assign disabled_clock$COND_IN_EN = 1'b0 ;
endmodule  // mkDefaultValue1