# Due to bugs in iverilog, we must use -no-use-negate and cannot do
# wide division.

test_c_veri_bsv SimpleTest sysSimpleTest.out.expected

test_c_veri_bsv_modules_options DivMod {} "-no-use-negate"

test_c_veri_bsv_modules_options DivModWide {} "-no-use-negate" sysDivModWide.out.expected

# expected status for darwin rh3 and rh4
set fpe [list SIGFPE 8 136]

# Test that divide-by-zero produces some failure in Bluesim
compile_object_pass DivideByZero.bsv sysDivideByZero
link_objects_pass sysDivideByZero sysDivideByZero
sim_output_status sysDivideByZero $fpe

# In Verilog it silently produces x's
test_veri_only_bsv DivideByZero sysDivideByZero.v.out.expected

# Test that divide-by-zero produces some failure in Bluesim
compile_object_pass DivideByZeroWide.bsv sysDivideByZeroWide
link_objects_pass sysDivideByZeroWide sysDivideByZeroWide
sim_output_status sysDivideByZeroWide $fpe

# In Verilog it silently produces x's
test_veri_only_bsv DivideByZeroWide sysDivideByZeroWide.v.out.expected

# Test that compile-time divide-by-zero produces a compile-time failure
compile_object_fail_error DivideByZeroStatic.bsv G0059 1 sysDivideByZeroStatic