Flags {
	aggImpConds = False,
	allowIncoherentMatches = False,
	backend = Nothing,
	bdir = Nothing,
	biasMethodScheduling = False,
	bluespecDir = "BLUESPECDIR",
	cDebug = False,
	cFlags = [],
	cIncPath = [],
	cLibPath = [],
	cLibs = [],
	cdir = Nothing,
	cpp = False,
	cppFlags = [],
	crossInfo = False,
	cxxFlags = [],
	defines = [],
	demoteErrors = SomeMsgs [],
	disableAssertions = False,
	doICheck = True,
	dumpAll = False,
	dumps = [],
	enablePoisonPills = False,
	entry = Nothing,
	expandATSlimit = 20,
	expandIf = False,
	extraVerbose = False,
	fdir = Nothing,
	finalcleanup = 1,
	genABin = False,
	genABinVerilog = False,
	genName = [],
	genSysC = False,
	ifLift = True,
	ifcPath = [".","BLUESPECDIR/Libraries"],
	ifcPathRaw = ["$DEFAULT_PATH"],
	infoDir = Nothing,
	inlineBool = True,
	inlineISyntax = True,
	inlineSimple = False,
	keepAddSize = False,
	keepFires = False,
	keepInlined = False,
	kill = Nothing,
	linkFlags = [],
	maxTIStackDepth = 1000,
	methodBVI = False,
	methodConditions = False,
	methodConf = False,
	neatNames = False,
	oFile = "a.out",
	optATS = True,
	optAggInline = True,
	optAndOr = True,
	optBitConst = False,
	optBool = False,
	optFinalPass = True,
	optIfMux = False,
	optIfMuxSize = 256,
	optJoinDefs = True,
	optMux = True,
	optMuxConst = True,
	optMuxExpand = False,
	optSched = True,
	optUndet = False,
	parallelSimLink = 1,
	passThroughAssertions = False,
	preprocessOnly = False,
	printFlags = False,
	printFlagsHidden = False,
	printFlagsRaw = True,
	promoteWarnings = SomeMsgs [],
	readableMux = True,
	redStepsMaxIntervals = 10,
	redStepsWarnInterval = 100000,
	relaxMethodEarliness = True,
	removeCReg = True,
	removeCross = True,
	removeEmptyRules = True,
	removeFalseRules = True,
	removeInoutConnect = True,
	removePrimModules = True,
	removeRWire = True,
	removeReg = True,
	removeStarvedRules = False,
	removeUnusedMods = False,
	removeVerilogDollar = False,
	resetName = "RST_N",
	resource = RFoff,
	rstGate = False,
	ruleNameCheck = True,
	satBackend = SAT_Yices,
	schedConds = False,
	schedDOT = False,
	schedQueries = [],
	showCSyntax = False,
	showCodeGen = False,
	showElabProgress = False,
	showIESyntax = False,
	showISyntax = False,
	showModuleUse = False,
	showRangeConflict = False,
	showSchedule = False,
	showStats = False,
	showUpds = True,
	showVersion = True,
	simplifyCSyntax = False,
	strictMethodSched = True,
	suppressWarnings = SomeMsgs [],
	synthesize = False,
	systemVerilogTasks = False,
	tclShowHidden = False,
	testAssert = False,
	timeStamps = True,
	unsafeAlwaysRdy = False,
	unSpecTo = "A",
	updCheck = False,
	useDPI = False,
	useNegate = True,
	usePrelude = True,
	useProvisoSAT = True,
	v95 = False,
	vFlags = [],
	vPath = [".","BLUESPECDIR/Libraries","BLUESPECDIR/Verilog"],
	vPathRaw = ["$DEFAULT_PATH"],
	vdir = Nothing,
	verbose = False,
	verilogDeclareAllFirst = True,
	verilogFilter = [],
	vpp = True,
	vsim = Nothing,
	warnActionShadowing = True,
	warnMethodUrgency = True,
	warnUndetPred = False
}