checking package dependencies
compiling InterfaceOrderingParallel.bs
code generation for sysInterfaceOrderingParallel starts
=== schedule:
parallel: [esposito: [act -> [], RL_write -> []]]
order: [act, RL_write]

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=== resources:
[(r.read, [(r.read, 1)]), (r.write, [(r.write 1'd0, 1)]), (r_1.write, [(r_1.write 1'd0, 1)])]

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=== vschedinfo:
SchedInfo [RDY_act CF [RDY_act, act], act SBR act] [] [] []

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Schedule dump file created: sysInterfaceOrderingParallel.sched
=== Generated schedule for sysInterfaceOrderingParallel ===

Method schedule
---------------
Method: act
Ready signal: r
Sequenced before (restricted): act
 
Rule schedule
-------------
Rule: write
Predicate: True
Blocking rules: (none)
 
Logical execution order: act, write

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Verilog file created: sysInterfaceOrderingParallel.v
All packages are up to date.