checking package dependencies
compiling Ex2.bsv
code generation for mkEx2 starts
=== schedule:
parallel: [esposito: [a -> [], c -> [], RL_b -> []]]
order: [a, RL_b, c]

-----

=== resources:
[(r1.write, [(r1.write r2__h234, 1)]),
 (r2.read, [(r2.read, 1)]),
 (r2.write, [(r2.write r3__h196, 1)]),
 (r3.read, [(r3.read, 1)]),
 (r3.write, [(r3.write 1'd1, 1)])]

-----

=== vschedinfo:
SchedInfo
[RDY_a CF [RDY_a, RDY_c, a, c], RDY_c CF [RDY_c, a, c], a SBR [a, c], c SBR c]
[((a, c), [RL_b])]
[(c, [(Left RL_b)])]
[]

-----

Schedule dump file created: mkEx2.sched
=== Generated schedule for mkEx2 ===

Method schedule
---------------
Method: a
Ready signal: True
Sequenced before (restricted): a, c
 
Method: c
Ready signal: True
Sequenced before (restricted): c
Sequenced after (restricted): a
 
Rule schedule
-------------
Rule: b
Predicate: True
Blocking rules: (none)
 
Logical execution order: a, b, c

=====================================
Verilog file created: mkEx2.v
All packages are up to date.