checking package dependencies
compiling Ex4.bsv
code generation for mkEx4 starts
=== schedule:
parallel: [esposito: [a -> [],
		      c -> [],
		      RL_b1 -> [],
		      RL_b2 -> [],
		      RL_b3 -> [],
		      RL_b4 -> [],
		      RL_b5 -> []]]
order: [a, RL_b1, RL_b2, RL_b3, RL_b4, RL_b5, c]

-----

=== resources:
[(r1.write, [(r1.write r2__h490, 1)]),
 (r2.read, [(r2.read, 1)]),
 (r2.write, [(r2.write r3__h394, 1)]),
 (r3.read, [(r3.read, 1)]),
 (r3.write, [(r3.write r4__h409, 1)]),
 (r4.read, [(r4.read, 1)]),
 (r4.write, [(r4.write r5__h424, 1)]),
 (r5.read, [(r5.read, 1)]),
 (r5.write, [(r5.write r6__h439, 1)]),
 (r6.read, [(r6.read, 1)]),
 (r6.write, [(r6.write r7__h452, 1)]),
 (r7.read, [(r7.read, 1)]),
 (r7.write, [(r7.write 1'd1, 1)])]

-----

=== vschedinfo:
SchedInfo
[RDY_a CF [RDY_a, RDY_c, a, c], RDY_c CF [RDY_c, a, c], a SBR [a, c], c SBR c]
[((a, c), [RL_b1, RL_b2, RL_b3, RL_b4, RL_b5])]
[(c, [(Left RL_b1), (Left RL_b2), (Left RL_b3), (Left RL_b4), (Left RL_b5)])]
[]

-----

Schedule dump file created: mkEx4.sched
=== Generated schedule for mkEx4 ===

Method schedule
---------------
Method: a
Ready signal: True
Sequenced before (restricted): a, c
 
Method: c
Ready signal: True
Sequenced before (restricted): c
Sequenced after (restricted): a
 
Rule schedule
-------------
Rule: b1
Predicate: True
Blocking rules: (none)
 
Rule: b2
Predicate: True
Blocking rules: (none)
 
Rule: b3
Predicate: True
Blocking rules: (none)
 
Rule: b4
Predicate: True
Blocking rules: (none)
 
Rule: b5
Predicate: True
Blocking rules: (none)
 
Logical execution order: a, b1, b2, b3, b4, b5, c

=====================================
Verilog file created: mkEx4.v
All packages are up to date.