checking package dependencies
compiling AddTest_sat-yices.bsv
code generation for sysAddTest starts
Warning: "AddTest_sat-yices.bsv", line 10, column 8: (G0010)
  Rule "aa" was treated as more urgent than "bb". Conflicts:
    "aa" cannot fire before "bb": calls to uc.write vs. uc.read
    "bb" cannot fire before "aa": calls to uc.write vs. uc.read
Warning: "AddTest_sat-yices.bsv", line 10, column 8: (G0010)
  Rule "ab" was treated as more urgent than "bb". Conflicts:
    "ab" cannot fire before "bb": calls to uc.write vs. uc.read
    "bb" cannot fire before "ab": calls to uc.write vs. uc.read
=== schedule:
parallel: [esposito: [RL_aa -> [], RL_ab -> [], RL_bb -> [RL_ab, RL_aa]]]
order: [RL_aa, RL_ab, RL_bb]

-----

=== resources:
[(ua.read, [(ua.read, 1)]),
 (ub.read, [(ub.read, 1)]),
 (uc.read, [(uc.read, 1)]),
 (uc.write,
  [(uc.write uc_PLUS_1___d6, 1), (uc.write uc_PLUS_2___d12, 1), (uc.write uc_PLUS_3___d15, 1)])]

-----

=== vschedinfo:
SchedInfo [] [] [] []

-----

Schedule dump file created: sysAddTest.sched
=== Generated schedule for sysAddTest ===

Rule schedule
-------------
Rule: aa
Predicate: (ua - ub) == 36'd17
Blocking rules: (none)
 
Rule: ab
Predicate: ! ((36'd1 + ua + (~ ub)) == 36'd17)
Blocking rules: (none)
 
Rule: bb
Predicate: ! (ua == 36'd0)
Blocking rules: ab, aa
 
Logical execution order: aa, ab, bb

==========================================
Warning: "AddTest_sat-yices.bsv", line 26, column 10: (G0021)
  According to the generated schedule, rule `bb' can never fire.
Verilog file created: sysAddTest.v
All packages are up to date.