checking package dependencies compiling ArraySelectLongIndexTest_sat-stp.bsv code generation for sysArraySelectLongIndexTest starts Warning: "ArraySelectLongIndexTest_sat-stp.bsv", line 9, column 8: (G0010) Rule "aa" was treated as more urgent than "bb". Conflicts: "aa" cannot fire before "bb": calls to uc.write vs. uc.read "bb" cannot fire before "aa": calls to uc.write vs. uc.read Warning: "ArraySelectLongIndexTest_sat-stp.bsv", line 9, column 8: (G0010) Rule "ab" was treated as more urgent than "bb". Conflicts: "ab" cannot fire before "bb": calls to uc.write vs. uc.read "bb" cannot fire before "ab": calls to uc.write vs. uc.read === schedule: parallel: [esposito: [RL_aa -> [], RL_ab -> [], RL_bb -> [RL_ab, RL_aa]]] order: [RL_aa, RL_ab, RL_bb] ----- === resources: [(idx.read, [(idx.read, 1)]), (rg_0.read, [(rg_0.read, 1)]), (rg_1.read, [(rg_1.read, 1)]), (rg_2.read, [(rg_2.read, 1)]), (rg_3.read, [(rg_3.read, 1)]), (rg_4.read, [(rg_4.read, 1)]), (uc.read, [(uc.read, 1)]), (uc.write, [(uc.write uc_1_PLUS_1___d12, 1), (uc.write uc_1_PLUS_2___d21, 1), (uc.write uc_1_PLUS_3___d22, 1)])] ----- === vschedinfo: SchedInfo [] [] [] [] ----- Schedule dump file created: sysArraySelectLongIndexTest.sched === Generated schedule for sysArraySelectLongIndexTest === Rule schedule ------------- Rule: aa Predicate: (idx < 3'd5) && (PrimArrayDynSelect (PrimBuildArray rg_0 rg_1 rg_2 rg_3 rg_4) idx) Blocking rules: (none) Rule: ab Predicate: (idx < 3'd5) && (PrimArrayDynSelect (PrimBuildArray (! rg_0) (! rg_1) (! rg_2) (! rg_3) (! rg_4)) idx) Blocking rules: (none) Rule: bb Predicate: idx < 3'd5 Blocking rules: ab, aa Logical execution order: aa, ab, bb =========================================================== Warning: "ArraySelectLongIndexTest_sat-stp.bsv", line 35, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysArraySelectLongIndexTest.v All packages are up to date.