checking package dependencies
compiling ArraySelectTest_sat-cudd.bsv
code generation for sysArraySelectTest starts
Warning: "ArraySelectTest_sat-cudd.bsv", line 6, column 8: (G0010)
  Rule "aa" was treated as more urgent than "bb". Conflicts:
    "aa" cannot fire before "bb": calls to uc.write vs. uc.read
    "bb" cannot fire before "aa": calls to uc.write vs. uc.read
Warning: "ArraySelectTest_sat-cudd.bsv", line 6, column 8: (G0010)
  Rule "ab" was treated as more urgent than "bb". Conflicts:
    "ab" cannot fire before "bb": calls to uc.write vs. uc.read
    "bb" cannot fire before "ab": calls to uc.write vs. uc.read
=== schedule:
parallel: [esposito: [RL_aa -> [], RL_ab -> [], RL_bb -> [RL_ab, RL_aa]]]
order: [RL_aa, RL_ab, RL_bb]

-----

=== resources:
[(idx.read, [(idx.read, 1)]),
 (rg_0.read, [(rg_0.read, 1)]),
 (rg_1.read, [(rg_1.read, 1)]),
 (rg_2.read, [(rg_2.read, 1)]),
 (rg_3.read, [(rg_3.read, 1)]),
 (uc.read, [(uc.read, 1)]),
 (uc.write,
  [(uc.write uc_PLUS_1___d9, 1), (uc.write uc_PLUS_2___d16, 1), (uc.write uc_PLUS_3___d18, 1)])]

-----

=== vschedinfo:
SchedInfo [] [] [] []

-----

Schedule dump file created: sysArraySelectTest.sched
=== Generated schedule for sysArraySelectTest ===

Rule schedule
-------------
Rule: aa
Predicate: PrimArrayDynSelect (PrimBuildArray rg_0 rg_1 rg_2 rg_3) idx
Blocking rules: (none)
 
Rule: ab
Predicate: PrimArrayDynSelect (PrimBuildArray (! rg_0)
					      (! rg_1)
					      (! rg_2)
					      (! rg_3))
			      idx
Blocking rules: (none)
 
Rule: bb
Predicate: idx == 2'd0
Blocking rules: ab, aa
 
Logical execution order: aa, ab, bb

==================================================
Warning: "ArraySelectTest_sat-cudd.bsv", line 32, column 10: (G0021)
  According to the generated schedule, rule `bb' can never fire.
Verilog file created: sysArraySelectTest.v
All packages are up to date.