checking package dependencies
compiling CaseTest_sat-cudd.bsv
code generation for sysCaseTest starts
Warning: "CaseTest_sat-cudd.bsv", line 6, column 8: (G0010)
  Rule "aa" was treated as more urgent than "bb". Conflicts:
    "aa" cannot fire before "bb": calls to uc.write vs. uc.read
    "bb" cannot fire before "aa": calls to uc.write vs. uc.read
Warning: "CaseTest_sat-cudd.bsv", line 6, column 8: (G0010)
  Rule "ab" was treated as more urgent than "bb". Conflicts:
    "ab" cannot fire before "bb": calls to uc.write vs. uc.read
    "bb" cannot fire before "ab": calls to uc.write vs. uc.read
=== schedule:
parallel: [esposito: [RL_aa -> [], RL_ab -> [], RL_bb -> [RL_ab, RL_aa]]]
order: [RL_aa, RL_ab, RL_bb]

-----

=== resources:
[(idx.read, [(idx.read, 1)]),
 (u0.read, [(u0.read, 1)]),
 (u1.read, [(u1.read, 1)]),
 (u2.read, [(u2.read, 1)]),
 (u3.read, [(u3.read, 1)]),
 (uc.read, [(uc.read, 1)]),
 (uc.write,
  [(uc.write uc_2_PLUS_1___d13, 1),
   (uc.write uc_2_PLUS_2___d21, 1),
   (uc.write uc_2_PLUS_3___d22, 1)])]

-----

=== vschedinfo:
SchedInfo [] [] [] []

-----

Schedule dump file created: sysCaseTest.sched
=== Generated schedule for sysCaseTest ===

Rule schedule
-------------
Rule: aa
Predicate: (idx == 2'd0)
	   ? u0
	   : ((idx == 2'd1)
	      ? u1
	      : ((idx == 2'd2)
		 ? u2
		 : u3))
Blocking rules: (none)
 
Rule: ab
Predicate: (idx == 2'd0)
	   ? ! u0
	   : ((idx == 2'd1)
	      ? ! u1
	      : ((idx == 2'd2)
		 ? ! u2
		 : (! u3)))
Blocking rules: (none)
 
Rule: bb
Predicate: idx == 2'd0
Blocking rules: ab, aa
 
Logical execution order: aa, ab, bb

===========================================
Warning: "CaseTest_sat-cudd.bsv", line 45, column 10: (G0021)
  According to the generated schedule, rule `bb' can never fire.
Verilog file created: sysCaseTest.v
All packages are up to date.