checking package dependencies
compiling DivTest_sat-yices.bsv
code generation for sysDivTest starts
Warning: "DivTest_sat-yices.bsv", line 10, column 8: (G0010)
  Rule "aa" was treated as more urgent than "bb". Conflicts:
    "aa" cannot fire before "bb": calls to uc.write vs. uc.read
    "bb" cannot fire before "aa": calls to uc.write vs. uc.read
Warning: "DivTest_sat-yices.bsv", line 10, column 8: (G0010)
  Rule "ab" was treated as more urgent than "bb". Conflicts:
    "ab" cannot fire before "bb": calls to uc.write vs. uc.read
    "bb" cannot fire before "ab": calls to uc.write vs. uc.read
Warning: "DivTest_sat-yices.bsv", line 10, column 8: (G0010)
  Rule "ac" was treated as more urgent than "bb". Conflicts:
    "ac" cannot fire before "bb": calls to uc.write vs. uc.read
    "bb" cannot fire before "ac": calls to uc.write vs. uc.read
Warning: "DivTest_sat-yices.bsv", line 10, column 8: (G0010)
  Rule "ad" was treated as more urgent than "bb". Conflicts:
    "ad" cannot fire before "bb": calls to uc.write vs. uc.read
    "bb" cannot fire before "ad": calls to uc.write vs. uc.read
Warning: "DivTest_sat-yices.bsv", line 10, column 8: (G0010)
  Rule "ae" was treated as more urgent than "bb". Conflicts:
    "ae" cannot fire before "bb": calls to uc.write vs. uc.read
    "bb" cannot fire before "ae": calls to uc.write vs. uc.read
=== schedule:
parallel: [esposito: [RL_aa -> [],
		      RL_ab -> [],
		      RL_ac -> [],
		      RL_ad -> [],
		      RL_ae -> [],
		      RL_af -> [],
		      RL_bb -> [RL_ae, RL_ad, RL_ac, RL_ab, RL_aa]]]
order: [RL_aa, RL_ab, RL_ac, RL_ad, RL_ae, RL_af, RL_bb]

-----

=== resources:
[(ua.read, [(ua.read, 1)]),
 (ub.read, [(ub.read, 1)]),
 (uc.read, [(uc.read, 1)]),
 (uc.write,
  [(uc.write uc_PLUS_2___d10, 1),
   (uc.write uc_PLUS_3___d20, 1),
   (uc.write uc_PLUS_1___d9, 1),
   (uc.write uc_MINUS_2___d24, 1),
   (uc.write uc_MINUS_1___d27, 1)])]

-----

=== vschedinfo:
SchedInfo [] [] [] []

-----

Schedule dump file created: sysDivTest.sched
=== Generated schedule for sysDivTest ===

Rule schedule
-------------
Rule: aa
Predicate: (! (ub == 2'd0)) && ((ua / ub) == 2'd1)
Blocking rules: (none)
 
Rule: ab
Predicate: ub == 2'd0
Blocking rules: (none)
 
Rule: ac
Predicate: (ua == 2'd1) && (! (ub < 2'd2))
Blocking rules: (none)
 
Rule: ad
Predicate: (! (ub == 2'd0)) && (ua == 2'd2) && (! (ub == 2'd2))
Blocking rules: (none)
 
Rule: ae
Predicate: (! (ub == 2'd0)) && (ua == 2'd3) && (ub < 2'd2)
Blocking rules: (none)
 
Rule: af
Predicate: (! (ub == 2'd0)) && (ua == 2'd0)
Blocking rules: (none)
 
Rule: bb
Predicate: ! (ua == 2'd0)
Blocking rules: ae, ad, ac, ab, aa
 
Logical execution order: aa, ab, ac, ad, ae, af, bb

==========================================
Warning: "DivTest_sat-yices.bsv", line 40, column 10: (G0021)
  According to the generated schedule, rule `bb' can never fire.
Verilog file created: sysDivTest.v
All packages are up to date.