checking package dependencies
compiling MultTest_sat-cudd.bsv
code generation for sysMultTest starts
Warning: "MultTest_sat-cudd.bsv", line 9, column 8: (G0010)
  Rule "aa" was treated as more urgent than "ab". Conflicts:
    "aa" cannot fire before "ab": calls to uc.write vs. uc.read
    "ab" cannot fire before "aa": calls to uc.write vs. uc.read
Warning: "MultTest_sat-cudd.bsv", line 9, column 8: (G0010)
  Rule "ab" was treated as more urgent than "bb". Conflicts:
    "ab" cannot fire before "bb": calls to uc.write vs. uc.read
    "bb" cannot fire before "ab": calls to uc.write vs. uc.read
=== schedule:
parallel: [esposito: [RL_aa -> [], RL_ab -> [RL_aa], RL_bb -> [RL_ab, RL_aa]]]
order: [RL_aa, RL_ab, RL_bb]

-----

=== resources:
[(ua.read, [(ua.read, 1)]),
 (ub.read, [(ub.read, 1)]),
 (uc.read, [(uc.read, 1)]),
 (uc.write,
  [(uc.write uc_PLUS_1___d9, 1), (uc.write uc_PLUS_2___d20, 1), (uc.write uc_PLUS_3___d23, 1)])]

-----

=== vschedinfo:
SchedInfo [] [] [] []

-----

Schedule dump file created: sysMultTest.sched
=== Generated schedule for sysMultTest ===

Rule schedule
-------------
Rule: aa
Predicate: ((12'd11 * ua)[11:0] * ub)[11:0] == 12'd17
Blocking rules: (none)
 
Rule: ab
Predicate: ! (((ub + {ub[10:0], 1'd0} + {ub[8:0], 3'd0}) * ua)[11:0] ==
	      12'd17)
Blocking rules: aa
 
Rule: bb
Predicate: ! (ua == 12'd0)
Blocking rules: ab, aa
 
Logical execution order: aa, ab, bb

===========================================
Verilog file created: sysMultTest.v
All packages are up to date.