checking package dependencies
compiling ParamBitsTest_sat-cudd.bsv
code generation for sysParamBitsTest starts
Warning: "ParamBitsTest_sat-cudd.bsv", line 5, column 8: (G0010)
  Rule "aa" was treated as more urgent than "bb". Conflicts:
    "aa" cannot fire before "bb": calls to uc.write vs. uc.read
    "bb" cannot fire before "aa": calls to uc.write vs. uc.read
Warning: "ParamBitsTest_sat-cudd.bsv", line 5, column 8: (G0010)
  Rule "ab" was treated as more urgent than "bb". Conflicts:
    "ab" cannot fire before "bb": calls to uc.write vs. uc.read
    "bb" cannot fire before "ab": calls to uc.write vs. uc.read
=== schedule:
parallel: [esposito: [RL_aa -> [], RL_ab -> [], RL_bb -> [RL_ab, RL_aa]]]
order: [RL_aa, RL_ab, RL_bb]

-----

=== resources:
[(uc.read, [(uc.read, 1)]),
 (uc.write,
  [(uc.write uc_PLUS_1___d3, 1), (uc.write uc_PLUS_2___d5, 1), (uc.write uc_PLUS_3___d6, 1)])]

-----

=== vschedinfo:
SchedInfo [] [] [] []

-----

Schedule dump file created: sysParamBitsTest.sched
=== Generated schedule for sysParamBitsTest ===

Rule schedule
-------------
Rule: aa
Predicate: p == 8'd17
Blocking rules: (none)
 
Rule: ab
Predicate: ! (p == 8'd17)
Blocking rules: (none)
 
Rule: bb
Predicate: True
Blocking rules: ab, aa
 
Logical execution order: aa, ab, bb

================================================
Warning: "ParamBitsTest_sat-cudd.bsv", line 19, column 9: (G0021)
  According to the generated schedule, rule `bb' can never fire.
Verilog file created: sysParamBitsTest.v
All packages are up to date.