checking package dependencies
compiling RemTest_sat-cudd.bsv
code generation for sysRemTest starts
Warning: "RemTest_sat-cudd.bsv", line 10, column 8: (G0010)
  Rule "aa" was treated as more urgent than "ab". Conflicts:
    "aa" cannot fire before "ab": calls to uc.write vs. uc.read
    "ab" cannot fire before "aa": calls to uc.write vs. uc.read
Warning: "RemTest_sat-cudd.bsv", line 10, column 8: (G0010)
  Rule "aa" was treated as more urgent than "ac". Conflicts:
    "aa" cannot fire before "ac": calls to uc.write vs. uc.read
    "ac" cannot fire before "aa": calls to uc.write vs. uc.read
Warning: "RemTest_sat-cudd.bsv", line 10, column 8: (G0010)
  Rule "aa" was treated as more urgent than "ad". Conflicts:
    "aa" cannot fire before "ad": calls to uc.write vs. uc.read
    "ad" cannot fire before "aa": calls to uc.write vs. uc.read
Warning: "RemTest_sat-cudd.bsv", line 10, column 8: (G0010)
  Rule "aa" was treated as more urgent than "ae". Conflicts:
    "aa" cannot fire before "ae": calls to uc.write vs. uc.read
    "ae" cannot fire before "aa": calls to uc.write vs. uc.read
Warning: "RemTest_sat-cudd.bsv", line 10, column 8: (G0010)
  Rule "ab" was treated as more urgent than "bb". Conflicts:
    "ab" cannot fire before "bb": calls to uc.write vs. uc.read
    "bb" cannot fire before "ab": calls to uc.write vs. uc.read
Warning: "RemTest_sat-cudd.bsv", line 10, column 8: (G0010)
  Rule "ad" was treated as more urgent than "bb". Conflicts:
    "ad" cannot fire before "bb": calls to uc.write vs. uc.read
    "bb" cannot fire before "ad": calls to uc.write vs. uc.read
Warning: "RemTest_sat-cudd.bsv", line 10, column 8: (G0010)
  Rule "ae" was treated as more urgent than "bb". Conflicts:
    "ae" cannot fire before "bb": calls to uc.write vs. uc.read
    "bb" cannot fire before "ae": calls to uc.write vs. uc.read
=== schedule:
parallel: [esposito: [RL_aa -> [],
		      RL_ab -> [RL_aa],
		      RL_ac -> [RL_aa],
		      RL_ad -> [RL_aa],
		      RL_ae -> [RL_aa],
		      RL_bb -> [RL_ae, RL_ad, RL_ab, RL_aa]]]
order: [RL_aa, RL_ab, RL_ac, RL_ad, RL_ae, RL_bb]

-----

=== resources:
[(ua.read, [(ua.read, 1)]),
 (ub.read, [(ub.read, 1)]),
 (uc.read, [(uc.read, 1)]),
 (uc.write,
  [(uc.write uc_PLUS_2___d11, 1),
   (uc.write uc_PLUS_3___d20, 1),
   (uc.write uc_PLUS_1___d9, 1),
   (uc.write uc_MINUS_2___d23, 1)])]

-----

=== vschedinfo:
SchedInfo [] [] [] []

-----

Schedule dump file created: sysRemTest.sched
=== Generated schedule for sysRemTest ===

Rule schedule
-------------
Rule: aa
Predicate: (! (ub == 2'd0)) && ((ua % ub) == 2'd1)
Blocking rules: (none)
 
Rule: ab
Predicate: ub <= 2'd1
Blocking rules: aa
 
Rule: ac
Predicate: (ua == 2'd0) && (! (ub <= 2'd1))
Blocking rules: aa
 
Rule: ad
Predicate: (ua == 2'd2) && ((ub == 2'd2) || (ub == 2'd3))
Blocking rules: aa
 
Rule: ae
Predicate: (ua == 2'd3) && (ub == 2'd3)
Blocking rules: aa
 
Rule: bb
Predicate: ! (ua == 2'd0)
Blocking rules: ae, ad, ab, aa
 
Logical execution order: aa, ab, ac, ad, ae, bb

==========================================
Verilog file created: sysRemTest.v
All packages are up to date.