checking package dependencies
compiling ShiftRATest_sat-cudd.bsv
code generation for sysShiftRATest starts
Warning: "ShiftRATest_sat-cudd.bsv", line 10, column 8: (G0010)
  Rule "aa" was treated as more urgent than "ab". Conflicts:
    "aa" cannot fire before "ab": calls to uc.write vs. uc.read
    "ab" cannot fire before "aa": calls to uc.write vs. uc.read
Warning: "ShiftRATest_sat-cudd.bsv", line 10, column 8: (G0010)
  Rule "ab" was treated as more urgent than "bb". Conflicts:
    "ab" cannot fire before "bb": calls to uc.write vs. uc.read
    "bb" cannot fire before "ab": calls to uc.write vs. uc.read
=== schedule:
parallel: [esposito: [RL_aa -> [], RL_ab -> [RL_aa], RL_bb -> [RL_ab, RL_aa]]]
order: [RL_aa, RL_ab, RL_bb]

-----

=== resources:
[(ua.read, [(ua.read, 1)]),
 (ub.read, [(ub.read, 1)]),
 (uc.read, [(uc.read, 1)]),
 (uc.write,
  [(uc.write uc_PLUS_1___d8, 1), (uc.write uc_PLUS_2___d26, 1), (uc.write uc_PLUS_3___d29, 1)])]

-----

=== vschedinfo:
SchedInfo [] [] [] []

-----

Schedule dump file created: sysShiftRATest.sched
=== Generated schedule for sysShiftRATest ===

Rule schedule
-------------
Rule: aa
Predicate: (ua >>>
	    (ub[17]
	     ? (_ :: Bit 18)
	     : ub)) ==
	   18'd17
Blocking rules: (none)
 
Rule: ab
Predicate: ! ((((ua[17] &&
		 (! (18'd1 <<
		     (ub[17]
		      ? (_ :: Bit 18)
		      : ub))[17])) ||
		((! ua[17]) &&
		 (18'd1 <<
		  (ub[17]
		   ? (_ :: Bit 18)
		   : ub))[17]))
	       ? - ((ua[17]
		     ? - ua
		     : ua) /
		    ((18'd1 <<
		      (ub[17]
		       ? (_ :: Bit 18)
		       : ub))[17]
		     ? - (18'd1 <<
			  (ub[17]
			   ? (_ :: Bit 18)
			   : ub))
		     : (18'd1 <<
			(ub[17]
			 ? (_ :: Bit 18)
			 : ub))))
	       : ((ua[17]
		   ? - ua
		   : ua) /
		  ((18'd1 <<
		    (ub[17]
		     ? (_ :: Bit 18)
		     : ub))[17]
		   ? - (18'd1 <<
			(ub[17]
			 ? (_ :: Bit 18)
			 : ub))
		   : (18'd1 <<
		      (ub[17]
		       ? (_ :: Bit 18)
		       : ub))))) ==
	      18'd17)
Blocking rules: aa
 
Rule: bb
Predicate: ! (ua == 18'd0)
Blocking rules: ab, aa
 
Logical execution order: aa, ab, bb

==============================================
Verilog file created: sysShiftRATest.v
All packages are up to date.